How to write UVM sequence items: rand fields and constraints, factory registration, do_copy, do_compare and convert2string vs field macros, and tips for scoreboard-friendly transactions.
Author: Raju Gorla
How a UVM testbench is structured: the component hierarchy, uvm_component vs uvm_object, building and connecting an environment, the top module and designing for reuse.
What UVM is, why it exists, its core classes, a minimal UVM test, and a learning path through my UVM series.
How latches change timing: transparent capture, time borrowing and how STA computes it, a worked example, set_max_time_borrow, and where latches appear in real designs.
Clock gating checks explained with a waveform: setup and hold on AND and OR gates, integrated clock gating cells, why enable paths are often critical, and other clock checks.
How to read a timing report, a step-by-step order for debugging setup and hold violations, useful report options, typical causes and fixes, and other violations to check.
How STA covers variation: PVT and RC corners, worst-case vs best-case analysis, temperature inversion, OCV derates, AOCV, POCV and LVF, and CRPR.
Timing exceptions explained: when to use false paths, how multicycle paths work (and why they need a hold adjustment), max delay and clock groups, and rules for writing safe exceptions.
SDC timing constraints explained: clocks, input and output delays, environment, exceptions, design rules and modes, a complete example, how to review an SDC and common mistakes.
How STA models clocks: source and network latency, skew and useful skew, jitter and clock uncertainty, clock definitions in SDC, and other clock checks.