17 Tcl interview questions for VLSI engineers with answers and scripts: substitution and quoting, lists and dicts, upvar, regexp, file handling, collections in EDA tools and report parsing.
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21 VHDL interview questions with answers and code: entity and architecture, signals vs variables, delta cycles, std_logic and numeric_std, synthesisable processes, FSMs and VHDL-2008.
18 Ethernet interview questions for VLSI roles with answers: frame format, 64-byte minimum, CRC, line rate, VLAN tags, MII interfaces, line coding, MAC design and verification.
21 DDR interview questions with answers: DRAM organisation, commands and timings, refresh, DDR4 vs DDR5, LPDDR and HBM, controller scheduling, DQS capture and PHY training.
22 PCIe interview questions with answers: topology and layers, TLP types, posted vs non-posted, ACK/NAK, flow control, generations, LTSSM, configuration space, BARs and MSI-X.
23 AXI interview questions with answers: the five channels, VALID/READY rules, burst types and limits, the 4 KB rule, IDs and ordering, responses, AXI4-Lite and Stream, and verification.
24 DFT interview questions with answers: fault models, scan design and DRC, ATPG and coverage, at-speed testing, compression, memory BIST, logic BIST and JTAG.
22 RTL synthesis interview questions with answers: the synthesis flow, coding style, optimisation, clock gating, multi-Vt cells, hierarchy and equivalence checking.
25 static timing analysis interview questions with answers: setup and hold, slack calculations, clocks, SDC constraints, multicycle paths, OCV, CRPR, crosstalk and PBA.
24 CDC and RDC interview questions with answers: metastability, synchronisers, pulse and multi-bit crossings, async FIFOs, constraints, reset synchronisers and reset domain crossings.