The short answer: STA handles variation in two layers. Global variation (the same for the whole die) is covered by corners: process (slow, typical, fast), voltage, temperature and RC extraction corners; setup is usually worst at slow corners and hold at fast ones. Local, on-chip variation (OCV) is covered by derating launch and capture paths in opposite directions, with flat derates, AOCV (by depth and distance) or POCV/LVF (a statistical sigma per cell). CRPR then removes pessimism on the clock path shared by launch and capture.
A chip is never built exactly at “typical”. Every die is a little different, and every transistor on a die is a little different. This post explains how STA covers both, without simulating millions of variations. It combines my older posts on worst-case and best-case timing analysis.
- The layers of variation
- Worst case and best case
- On-chip variation (OCV)
- AOCV and POCV
- CRPR
- Practical tips
Table of Contents
Part 1: The layers of variation
Part 2: Worst case and best case
| Analysis | Uses | Checks |
|---|---|---|
| Worst case (max) | Slow process, low voltage, the slow temperature, max-delay RC | Setup, max transition, max capacitance |
| Best case (min) | Fast process, high voltage, fast temperature, min-delay RC | Hold, min pulse checks |
| Typical | Nominal everything | Power estimates, not sign-off |
At older nodes “worst case” simply meant slow, low voltage and hot. At advanced nodes, temperature inversion can make cold the slowest corner, so both temperatures are analysed. In practice, sign-off runs every check in every relevant corner, because skewed paths can be worst somewhere unexpected.
Part 3: On-chip variation (OCV)
Even at one corner, cells on the same die differ slightly. For a setup check, OCV makes the launch clock and data path slower (late derate) and the capture clock faster (early derate); for hold, the reverse. That covers the worst case where local variation conspires against the path.
set_timing_derate -late 1.05 -cell_delay ;# +5% on late paths
set_timing_derate -early 0.95 -cell_delay ;# -5% on early pathsPart 4: AOCV and POCV
- Flat derates are pessimistic for long paths, because random variation partly averages out over many stages.
- AOCV uses tables of derates by logic depth and physical distance: deep paths get smaller derates.
- POCV with LVF (Liberty Variation Format) gives each cell arc a mean and sigma, and STA combines them statistically along the path. It’s the standard at advanced nodes.
Part 5: CRPR
The launch and capture clock paths usually share their first part (the root of the tree). OCV derates that shared part both late (for launch) and early (for capture) at the same time, which can’t happen physically. Clock reconvergence pessimism removal adds that difference back. Without CRPR, many paths with deep shared clock trees would fail falsely.
Part 6: Practical tips
- Know which corner each report comes from before acting on it.
- Fix setup at the slow corners and hold at the fast corners, then re-check both everywhere.
- Use PBA on the remaining violators near sign-off to remove graph-based pessimism.
- More at block level in sign-off timing and MCMM.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Static Timing Analysis problems · Daily challenge
Previous in my STA series: False paths and multicycle paths. Next: Reading timing reports and debugging violations.
FAQ
What is the difference between worst-case and best-case analysis?
Worst-case analysis uses slow conditions to check setup and max-delay limits; best-case analysis uses fast conditions to check hold.
What is OCV in STA?
On-chip variation: modelling local differences between cells on the same die by derating launch and capture paths in opposite directions.
What is the difference between AOCV and POCV?
AOCV uses derate tables by path depth and distance; POCV uses a statistical sigma per cell arc and combines them along the path.
What is CRPR?
Clock reconvergence pessimism removal: correcting for OCV derates applied in both directions to the clock path shared by launch and capture.
