The short answer: A latch is transparent while its enable is active, so data that arrives after the latch opens but before it closes still passes through. STA treats the opening edge as the nominal capture point; if data arrives later, the path borrows the extra time from the next stage, up to the closing edge minus the latch setup time. Time borrowing lets latch-based designs balance uneven pipeline stages, but the borrowed time must be repaid by the following path, and the analysis is more complex than for flip-flops.
Most ASIC designs are flip-flop based, but latches appear in clock gating cells, in some high-performance datapaths and in designs that use two-phase clocking. Understanding time borrowing is also a favourite interview topic. This is the last post in my STA series.
- How a latch passes late data
- Flip-flop vs latch timing
- How STA computes borrowing
- An example
- Where you meet latches in practice
Table of Contents
Part 1: How a latch passes late data
Part 2: Flip-flop vs latch timing
| Flip-flop | Latch | |
|---|---|---|
| Captures | At one edge | During the transparent phase |
| Late data | Setup violation | Passes through, borrowing time (until the closing edge) |
| Stage balancing | Each stage must fit in one cycle | A slow stage can borrow from a fast neighbour |
| Analysis | Simple | Needs borrow tracking across stages |
Part 3: How STA computes borrowing
- The path to a latch is first checked against the latch’s opening edge. If data arrives before it, there’s no borrowing and the next path starts from the opening edge.
- If data arrives after the opening edge but before (closing edge − setup), the difference is borrowed time. The next path starts from the actual arrival time, so it has that much less time.
- If data arrives after (closing edge − setup), it’s a real setup violation.
- You can limit borrowing with
set_max_time_borrow, which many teams do to keep analysis predictable.
Part 4: An example
Clock period 2.0 ns, latch transparent while clk is high (0.0 to 1.0 ns),
latch setup 0.05 ns.
Path A (flop -> latch) arrives at 0.40 ns
-> after the opening edge (0.0), before 1.0 - 0.05 = 0.95
-> borrows 0.40 ns
Path B (latch -> flop, next cycle edge at 2.0 ns) now starts at 0.40 ns
instead of 0.0 ns, so it has 0.40 ns less time.Part 5: Where you meet latches in practice
- Clock gating cells: the ICG’s latch holds the enable while the clock is high (see clock gating checks).
- High-speed datapaths: two-phase latch designs to balance pipeline stages.
- Lockup latches in scan chains between clock domains.
- Unintended latches from incomplete combinational RTL, which are bugs; see writing combinational logic.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Previous in my STA series: Clock gating checks. That’s the end of my STA series. For sign-off at block level, see sign-off timing and MCMM.
FAQ
What is time borrowing?
When data arrives at a transparent latch after it opens but before it closes, it passes through, effectively borrowing time from the next pipeline stage.
How much time can a path borrow?
Up to the latch’s closing edge minus its setup time, or less if limited with set_max_time_borrow.
Why are latches rarely used in ASIC designs?
Timing analysis, testing and debugging are more complex than with flip-flops, though latches can save area and help balance pipelines.
Does time borrowing hide timing problems?
It moves them. Borrowed time must be repaid by the next stage, so STA checks the whole chain.
