Learn chip design.
Then prove you can do it.
Clear guides on RTL, verification, timing and physical design, written by working engineers. When you finish reading, practise the same topic on VLSI Forge: write the code, run it on a real simulator, and watch every signal.
900+ engineers practising · 150+ free articles · no install needed
module counter ( input clk, input rst, input en, output reg [3:0] count ); always @(posedge clk) begin if (rst) count <= 4'd0; else if (en) count <= count + 4'd1; end endmodule
Free tutorials, by topic.
From your first logic gate to timing sign-off. Pick a topic and read in order, or jump to what you need.
Digital Circuits
Gates, flip-flops, adders, FSMs and timing basics.
Verilog
RTL coding, blocking vs non-blocking, testbenches.
SystemVerilog
Interfaces, classes, randomisation, assertions, coverage.
RTL Design
Synthesisable design, CDC, FIFOs and design reviews.
UVM
Components, sequences, phasing and the factory.
Physical Design
Floorplan, placement, CTS, routing and sign-off.
Static Timing
Setup, hold, constraints, OCV and timing closure.
Interview Questions
CDC, STA, DFT, synthesis, AXI, PCIe, DDR and more.
Careers & Industry
Roles, roadmaps, companies, tools and trends.
Write RTL. Watch it run.
The problems asked in VLSI interviews, auto-graded on Verilator, Icarus and GHDL. Every submission shows pass or fail per test and the full waveform. Free with an account.
RTL Design
50 problems
Design Verification
25 problems
SVA & Constraints
25 problems
CDC & RDC
25 problems
Static Timing Analysis
25 problems
Physical Design
25 problems
DFT
25 problems
FPGA Design
25 problems
Debug & Analysis
25 problems
Build something real, step by step.
Each course is a series of problems that adds up to one working design. The first 3 problems of every course are free.
CPU Design
Build a working RISC-V (RV32I) processor, run real programs on it, then pipeline it.
3 freeNPU Design
The silicon behind AI: MAC units, systolic arrays and INT8 datapaths.
3 freePhysical Design Closure
From floorplan to sign-off: congestion, timing, power and ECOs.
Fresh on VLSI Web.
Tcl Scripting for Physical Design: Queries, Floorplans and Flows
Advanced Nodes and 3D ICs: FinFET, GAA, Backside Power and Chiplets
Tape-Out and Mask Data Preparation: From Layout to Masks
PPA and Low-Power Physical Design: Optimising Power and Area
Physical Verification: DRC, LVS, ERC, Antenna and DFM Checks
IR Drop and Electromigration in Physical Design
Preparing for a VLSI interview?
Question-by-question guides for the topics interviewers ask most, with answers you can explain out loud.
A simple 3-step plan
- Read the guide for your target role here on VLSI Web.
- Solve the matching problems on VLSI Forge until you can write the RTL without notes.
- Check your skill score on Forge to find your weakest domain, then repeat.
Common questions
What is VLSI design?
VLSI (Very Large Scale Integration) design is how integrated circuits with millions to billions of transistors are built. Engineers describe the logic in a hardware description language such as Verilog, SystemVerilog or VHDL, verify it, then turn it into a physical layout that a foundry can manufacture.
What is the difference between VLSI Web and VLSI Forge?
VLSI Web is where you learn: free tutorials and interview guides across RTL, verification, timing and physical design. VLSI Forge is where you practise: you write RTL in the browser, it runs on a real simulator, and you see the waveform and whether every test passed.
Is VLSI Forge free?
Yes. All practice problems are free with a free account. Guided courses (CPU, NPU, Physical Design Closure) let you try the first 3 problems free before you decide.
Which simulators and languages does VLSI Forge use?
Verilog and SystemVerilog run on Verilator and Icarus Verilog, and VHDL runs on GHDL. Results show a pass or fail per test case plus the waveform of every signal.
How should I prepare for a VLSI interview?
Pick your target role (design, verification, physical design, STA or DFT), read the matching interview-question guide here, then solve problems in that domain on VLSI Forge until you can write the RTL without notes. Interviewers care more about clear reasoning on CDC, timing and reset than about memorised answers.
Do I need EDA tools installed to practise?
No. Everything runs in the browser. You can practise on a laptop or a phone without installing a simulator or licensing a commercial tool.
Read it here. Build it on Forge.
Free account, nothing to install, works on your phone.