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dff.v — VLSI Forge
1// D Flip-Flop with synchronous reset
2module dff (
3 input logic clk, rst_n, d,
4 output logic q
5);
6 always_ff @(posedge clk)
7 if (!rst_n) q <= 1'b0;
8 else q <= d;
9endmodule
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