The main low-power design techniques explained: clock gating, operand isolation, multi-Vt cells, power gating with isolation and retention, multi-voltage, DVFS, UPF and low-power verification.
Browsing: RTL Design
How teams sign off clock domain crossings: clock setup, structural CDC checks, waivers, assertions and formal, and the STA constraints that go with them.
What reset domain crossing is, why it causes metastability, the reset synchroniser with Verilog, and how to fix and check RDC issues.
How to calculate FIFO depth for bursts and different clock rates, with three worked examples and common mistakes.
How a synchronous FIFO works, two ways to generate full and empty, complete Verilog, and the corner cases to test.
How an asynchronous FIFO works: Gray-coded pointers, synchronisers, full and empty logic, complete Verilog and common mistakes.
How req/ack handshakes move multi-bit data safely across clock domains, with waveforms and Verilog for both sides.
Clock domain crossing explained: metastability and MTBF, two-flop and toggle synchronisers with Verilog, and how to handle multi-bit signals safely.
Clock domains, metastability, two-flop synchronisers, pulse and handshake synchronisers, async FIFOs, clock gating and reset synchronisation explained.