The short answer: A clock gating check makes sure the enable of a gate on a clock path changes only when it can’t chop or glitch the clock. For an AND-type gate, the enable must be stable while the clock is high, so STA applies a setup check before the clock’s rising edge and a hold check after its falling edge; for an OR-type gate, the opposite phase. Integrated clock gating (ICG) cells contain a latch that holds the enable while the clock is high, and their timing is checked through the cell’s own setup and hold arcs.
Clock gating is the most effective way to save dynamic power, but a gate in the clock path is also an easy way to create glitches that clock registers twice or not at all. STA protects against this with clock gating checks. This post replaces my older clock gating analysis post.
- The problem
- Clock gating setup and hold
- Integrated clock gating cells
- Why gating paths are often critical
- Other clock checks
Table of Contents
Part 1: The problem
Part 2: Clock gating setup and hold
| Gate type | Enable must be stable while | Setup check against | Hold check against |
|---|---|---|---|
| AND / NAND | clock is high | rising (leading) edge | falling (trailing) edge |
| OR / NOR | clock is low | falling edge | rising edge |
STA infers these checks automatically on simple gates in clock paths. You can set margins with set_clock_gating_check -setup 0.05 -hold 0.05.
Part 3: Integrated clock gating cells
An ICG cell combines a latch (transparent while the clock is low) with an AND gate. The latch captures the enable while the clock is low and holds it while the clock is high, so the gated clock can’t glitch even if the enable changes later. STA checks the enable against the ICG’s setup and hold arcs from its library. Because the enable path ends at the ICG, often one or two levels up the clock tree, it gets less time than a normal register path: the ICG’s clock arrives earlier than the flops it drives.
Part 4: Why gating paths are often critical
- The enable is captured at the ICG’s clock pin, which is earlier in the tree than the flops, so the effective period is shortened by the latency difference.
- Enables are often computed from deep control logic.
- Fixes: generate the enable one cycle early, place the ICG close to its enable logic, or clone the ICG so each copy sits lower in the tree.
Part 5: Other clock checks
- Minimum pulse width: high and low phases long enough for every flop.
- Clock-as-data: when a clock drives a data pin, which usually signals a design problem.
- Clock mux checks: muxes switching between clocks need glitch-free design and the right clock groups.
Clock gating cells are inserted during synthesis and placed during CTS; see clock tree synthesis.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Static Timing Analysis problems · Daily challenge
Previous in my STA series: Reading timing reports and debugging violations. Next: Latch timing and time borrowing.
FAQ
What is a clock gating check?
A setup and hold check on the enable of a gate in the clock path, ensuring the enable doesn’t change while it could chop or glitch the clock.
When must the enable of an AND clock gate be stable?
While the clock is high: setup before the rising edge and hold after the falling edge.
Why use ICG cells?
Their internal latch holds the enable while the clock is high, so the gated clock can’t glitch.
Why are clock gating enable paths often timing-critical?
The ICG’s clock arrives earlier than the flops it drives, so the enable logic gets less time than a normal register path.
