How SystemVerilog testbench threads work: fork-join, join_any and join_none, the classic loop bug, mailboxes, semaphores, events, disable fork and wait fork.
Author: Raju Gorla
SystemVerilog constrained randomisation explained: rand and randc, constraint blocks, dist, implication, foreach, unique, soft, solve before, inline constraints and common mistakes.
SystemVerilog classes for testbenches: objects and handles, shallow vs deep copy, encapsulation, inheritance, virtual methods and polymorphism, abstract classes and parameterised classes.
SystemVerilog interfaces explained with a complete example: modports, clocking blocks with skews, assertions inside interfaces, virtual interfaces and parameterised interfaces.
What SystemVerilog adds to tasks and functions: return, void functions, default and named arguments, ref and const ref, typed arguments and automatic storage, with examples.
The SystemVerilog features I use in synthesisable RTL: always_ff and always_comb, unique and priority, packages, enums and structs, and what synthesis does with each.
SystemVerilog data types explained: logic vs bit, 2-state and 4-state types, enums, packed structs and unions, packed vs unpacked arrays, dynamic arrays, queues and associative arrays.
What SystemVerilog is, how it extends Verilog for RTL design and verification, a short history, what each role needs to learn, and a learning path.
Clock domains, metastability, two-flop synchronisers, pulse and handshake synchronisers, async FIFOs, clock gating and reset synchronisation explained.
UVM reporting explained: the four message macros, verbosity levels, IDs and actions, command-line controls, report catchers, the report server summary and habits for readable logs.