UVM callbacks explained step by step: defining, registering and calling hooks in a component, extending and adding them from a test, error injection, and callbacks vs factory overrides.
Author: Raju Gorla
The UVM register model explained: register model hierarchy, generation, the adapter, explicit prediction, front-door and back-door access, the access API and built-in register sequences.
How functional coverage and assertions fit into a UVM testbench: coverage subscribers, configurable collection, scenario coverage, assertions in interfaces reporting through UVM, and coverage closure.
How to write a UVM scoreboard: predictor and reference model, in-order and out-of-order expected stores, comparison, end-of-test checks and mistakes that hide bugs.
UVM TLM explained: ports, exports and imps, put and get, analysis ports and subscribers, uvm_analysis_imp_decl, analysis FIFOs and how monitors feed scoreboards and coverage.
How UVM configuration works: uvm_config_db set and get, passing virtual interfaces, configuration objects, paths and precedence, the command-line processor and common mistakes.
How the UVM factory works: registration macros, type_id::create, type and instance overrides, command-line overrides, debugging the factory and mistakes that silently break overrides.
UVM phases explained: build, connect, run, extract, check and report, what goes in each phase, objections and drain time, run-time sub-phases and common mistakes.
How to build a reusable UVM agent: the driver, the monitor with an analysis port, the agent with active and passive modes, and rules that make agents reusable.
UVM sequences and sequencers explained: the start_item/finish_item handshake, the driver side, starting sequences from tests, nested and parallel sequences, lock and grab, and virtual sequences.