The Verilog coding guidelines I follow for synthesisable RTL: clocks, resets, combinational and sequential logic, synthesis rules, readability and lint.
Browsing: Verilog
The Verilog system tasks I actually use: $display vs $strobe vs $monitor, format specifiers, $finish, file I/O, $readmemh, waveform dumping, $random and $clog2.
How and when to use parameter, localparam and `define in Verilog, with examples, macro pitfalls, include guards, conditional compilation and other compiler directives.
Verilog tasks vs functions explained with examples: return values, timing controls, synthesis, how arguments are passed, and static vs automatic.
How delays work in Verilog: timescale, inter vs intra-assignment delays, inertial vs transport delays with waveforms, rise and fall delays, specify blocks and $setup, $hold and $width.
How to code FSMs in Verilog: the three parts of a state machine, a complete traffic light controller, one vs two vs three-block styles, state encoding and common mistakes.
Verilog templates for flip-flops (async and sync reset, enable), latches, registers, shift registers, pipelines and counters, with rules for sequential blocks.
How to write combinational logic in Verilog: a five-step checklist, ALU, priority encoder, decoder and mux examples, avoiding latches and loops, and thinking about timing.
Verilog if-else, case, casez and loops explained with the hardware they create: priority logic, muxes, unrolled loops, and how to avoid latches.
Blocking (=) vs non-blocking (<=) assignments explained with waveforms, the Verilog scheduling regions behind them, race conditions, and the rules to follow in RTL.