The short answer: Timing exceptions tell STA that a path shouldn’t be timed the default single-cycle way. A false path (set_false_path) is never timed, for example between asynchronous clocks or from a static configuration register. A multicycle path (set_multicycle_path) is still timed but allowed more than one cycle; when you move the setup check by N cycles, you usually also move the hold check back by N−1 so hold stays on the launch edge. Exceptions should be few, narrow and justified, because a wrong one hides real failures.
Exceptions are the most dangerous lines in an SDC. A single over-broad false path can switch off timing on hundreds of real paths without a single warning. This post explains how false and multicycle paths work and how I write them safely. It combines my older posts on false paths and multicycle paths.
- False paths
- Multicycle paths
- Other exceptions
- Rules I follow for exceptions
Table of Contents
Part 1: False paths
- Paths between asynchronous clock domains (better expressed as set_clock_groups -asynchronous).
- Paths from quasi-static signals: configuration registers written once while the destination is idle.
- Paths that can’t be sensitised functionally, such as between two muxes that are never selected together (prove this before declaring it).
- Test-only paths when timing a functional mode, handled with case analysis or mode-specific SDC.
set_clock_groups -asynchronous -group {clk_a} -group {clk_b}
set_false_path -from [get_cells u_cfg/mode_reg*] ;# static after boot, see spec 4.2False-pathing a CDC crossing doesn’t make it safe; it only stops STA from timing it. The crossing still needs a proper synchroniser.
Part 2: Multicycle paths
set_multicycle_path 2 -setup -from [get_cells u_mac/acc_in*] -to [get_cells u_mac/acc_out*]
set_multicycle_path 1 -hold -from [get_cells u_mac/acc_in*] -to [get_cells u_mac/acc_out*]- The -setup 2 moves the setup check to the second capture edge.
- By default, the hold check moves with it (to one edge before the new setup edge), which would make hold far too strict.
- The -hold 1 moves the hold check back by one edge, to the original launch edge.
- Only use a multicycle path when the design guarantees it, typically with an enable that captures every N cycles; otherwise it’s a functional bug waiting to happen.
Part 3: Other exceptions
| Command | Use |
|---|---|
| set_max_delay / set_min_delay | Point-to-point limits, e.g. async FIFO Gray pointers (-datapath_only) |
| set_clock_groups -physically_exclusive | Clocks that can never exist at the same time (muxed clocks) |
| set_clock_groups -logically_exclusive | Clocks that exist together but never interact |
| set_disable_timing | Break a timing arc, e.g. a loop in a scan path |
Part 4: Rules I follow for exceptions
- Be specific: -from and -to on exact registers or pins, never wildcards like *reg*.
- Comment every exception with the reason and a reference to the spec.
- Review exceptions with the RTL designer who owns the logic.
- Check exceptions are actually applied: tools report unused or overridden exceptions.
- Prefer architectural fixes (pipelining, synchronisers) over exceptions when possible.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Previous in my STA series: SDC timing constraints. Next: Corners, OCV and variation.
FAQ
What is a false path?
A timing path that STA should ignore because it can never be exercised in a timing-critical way, such as a path between asynchronous clocks or from a static register.
What is a multicycle path?
A path that is allowed more than one clock cycle for data to propagate, usually because the capture register is enabled every N cycles.
Why do we need set_multicycle_path -hold with -setup?
Moving the setup check also moves the default hold check forward, making it too strict. The hold multicycle moves it back to the original edge.
Is a false path on a CDC enough?
No. It stops STA from timing the path, but the crossing still needs a synchroniser or FIFO to be safe.
