The short answer: SDC (Synopsys Design Constraints) is the Tcl-based format that tells synthesis, place-and-route and STA tools what timing to meet. A complete SDC defines every clock (and generated clock), the input and output delays that describe the world outside the block, the environment (driving cells, loads), timing exceptions (false paths, multicycle paths, clock groups), design rule limits and mode settings. STA is only as correct as its constraints, so reviewing the SDC is one of the most important sign-off tasks.
I’ve seen more timing escapes caused by wrong constraints than by wrong analysis. A missing clock, an input delay on the wrong clock, or a false path that’s too broad can hide real failures completely. This post walks through a complete SDC and how I check one. It replaces my older timing constraints post.
- The groups
- A small, complete SDC
- Input and output delays, explained
- How I review an SDC
- Common SDC mistakes
Table of Contents
Part 1: The groups
Part 2: A small, complete SDC
# clocks
create_clock -name clk -period 2.0 [get_ports clk]
set_clock_uncertainty -setup 0.10 [get_clocks clk]
set_clock_uncertainty -hold 0.05 [get_clocks clk]
# I/O: outside logic uses 0.8 ns of the cycle before our inputs
set_input_delay -clock clk -max 0.8 [remove_from_collection [all_inputs] [get_ports clk]]
set_input_delay -clock clk -min 0.1 [remove_from_collection [all_inputs] [get_ports clk]]
# outside logic needs our outputs 0.6 ns before its capture edge
set_output_delay -clock clk -max 0.6 [all_outputs]
set_output_delay -clock clk -min 0.0 [all_outputs]
# environment
set_driving_cell -lib_cell BUFX4 [all_inputs]
set_load 0.02 [all_outputs]
# design rules
set_max_transition 0.15 [current_design]
set_max_fanout 32 [current_design]
# exceptions
set_false_path -from [get_ports rst_n] ;# synchronised inside the blockPart 3: Input and output delays, explained
- set_input_delay says how long after the clock edge the data arrives at the input port, from logic outside the block. The remaining part of the period is what’s available inside.
- set_output_delay says how much time the external logic needs before its capture edge, so the output must be ready that much before the edge.
- Use -max for setup and -min for hold. Missing -min values often hide hold problems at block boundaries.
- At block level, these values usually come from the top-level timing budget.
Part 4: How I review an SDC
- check_timing: no unconstrained endpoints, no unclocked registers, no missing input or output delays.
- Every clock in the design is defined, including generated clocks at dividers and muxes.
- Clock relationships are right: synchronous clocks timed together, asynchronous ones in separate clock groups.
- Every exception has a comment explaining why, and is as narrow as possible (specific -from and -to).
- The same SDC (per mode) is used in synthesis, P&R and sign-off.
Part 5: Common SDC mistakes
| Mistake | Effect |
|---|---|
| Clock not defined on a generated clock pin | Paths through it unconstrained or timed wrongly |
| Wildcard false path (-from *reg*) | Hides real paths |
| Input delay relative to the wrong clock | Wrong setup and hold at the boundary |
| No set_output_delay on outputs | Output paths not timed at all |
| Multicycle without the matching hold adjustment | Hold far too strict, causing needless buffering |
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Previous in my STA series: Clocks in STA: latency, skew, jitter. Next: False paths and multicycle paths.
FAQ
What is SDC?
Synopsys Design Constraints: a Tcl-based format describing clocks, I/O timing, environment, exceptions and design rules for timing-driven tools.
What does set_input_delay mean?
The time after a clock edge at which data arrives at an input port from outside the block, which limits how much of the cycle is available inside.
What is check_timing used for?
To find constraint problems such as unconstrained endpoints, unclocked registers and missing I/O delays.
Should synthesis and sign-off use the same SDC?
Yes, per mode, with only intended differences (such as ideal vs propagated clocks). Mismatches cause timing surprises late in the flow.
