Author: Raju Gorla

What setup and hold time mean, the timing equations, how to fix each kind of violation, and the link to metastability.

How D, JK, T and SR flip-flops work, their characteristic tables, edge triggering, and Verilog for each.

How SR and D latches work, how they differ from flip-flops, and how to avoid accidental latches in Verilog.

What sequential logic is, the structure of synchronous circuits, synchronous vs asynchronous design, and how to write sequential RTL.

How decoders, encoders and priority encoders work, one-hot encoding, and Verilog for each.

How multiplexers and demultiplexers work, using a mux as universal logic, and Verilog examples.

Comparators, array, Booth and Wallace-tree multipliers, and how an ALU works, with Verilog.

Half and full adders, ripple-carry vs carry-lookahead, subtraction with two’s complement, and adders in Verilog.

What combinational logic is, the five-step design process, a worked majority-voter example in Verilog, and common pitfalls.

How CMOS gates are built from PMOS and NMOS transistors, NAND vs NOR, where power goes, and how logic families compare.