The short answer: sequential logic has memory: its outputs depend on the current inputs and on stored state. Almost all modern chips use synchronous sequential design, where every flip-flop updates on the edge of a clock. That gives you a simple, predictable structure: combinational logic computes the next state, flip-flops store it, and timing analysis only has to check paths between flops. Asynchronous (clockless) design exists, but it is much harder to design and verify.
This post is the starting point for the sequential topics on this site, and replaces my older posts on sequential circuits and synchronous vs asynchronous circuits.
- The structure of every synchronous circuit
- Synchronous vs asynchronous circuits
- Writing sequential logic in Verilog
- The sequential building blocks
Table of Contents
Part 1: The structure of every synchronous circuit
Part 2: Synchronous vs asynchronous circuits
| Synchronous | Asynchronous | |
|---|---|---|
| State changes | Only on clock edges | Whenever inputs change |
| Timing analysis | Straightforward (flop to flop) | Hard; races and hazards |
| Design and verification | Well supported by tools | Specialist techniques |
| Where used | Almost all digital chips | Niche low-power or high-speed blocks |
In practice, “asynchronous” in everyday RTL work usually means something else: signals crossing between unrelated clocks. That is covered in clock domain crossing.
Part 3: Writing sequential logic in Verilog
// The standard template: one clocked block for state,
// combinational logic computed separately
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
q <= '0;
else if (en)
q <= d; // non-blocking for sequential logic
end- Use non-blocking assignments (<=) in clocked blocks.
- Keep each register in exactly one always block.
- Decide your reset style once and use it consistently. See synchronous vs asynchronous reset.
Part 4: The sequential building blocks
- Latches vs flip-flops
- Flip-flops: D, JK, T and SR
- Setup and hold time
- Mealy and Moore state machines
- Counters and clock dividers
- Registers and shift registers
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
FAQ
What is the difference between combinational and sequential logic?
Combinational outputs depend only on current inputs. Sequential outputs also depend on stored state, held in flip-flops or latches.
Why is synchronous design preferred?
It makes timing predictable and analysable, which lets tools and engineers build and verify very large designs reliably.
Is a clock always needed for sequential logic?
Synchronous logic needs one. Latches and asynchronous circuits can store state without a clock edge, but they are used much less.
What is the maximum clock frequency of a synchronous design?
It is set by the slowest flop-to-flop path: clock-to-Q plus logic delay plus setup time, adjusted for skew.
