Author: Raju Gorla

What reset domain crossing is, why it causes metastability, the reset synchroniser with Verilog, and how to fix and check RDC issues.

How to calculate FIFO depth for bursts and different clock rates, with three worked examples and common mistakes.

How a synchronous FIFO works, two ways to generate full and empty, complete Verilog, and the corner cases to test.

How an asynchronous FIFO works: Gray-coded pointers, synchronisers, full and empty logic, complete Verilog and common mistakes.

How req/ack handshakes move multi-bit data safely across clock domains, with waveforms and Verilog for both sides.

Clock domain crossing explained: metastability and MTBF, two-flop and toggle synchronisers with Verilog, and how to handle multi-bit signals safely.

How registers and shift registers work, the four shift register types, Verilog including an LFSR, and where they are used.

Binary, modulo-N, ring, Johnson and Gray counters, a modulo-N counter in Verilog, and how to divide clocks safely.

Mealy vs Moore FSMs compared with state diagrams, a clean Verilog template, state encoding and design tips.

Synchronous vs asynchronous reset compared, Verilog for each, how to release reset safely, and what to reset.