Author: Raju Gorla

25 static timing analysis interview questions with answers: setup and hold, slack calculations, clocks, SDC constraints, multicycle paths, OCV, CRPR, crosstalk and PBA.

24 CDC and RDC interview questions with answers: metastability, synchronisers, pulse and multi-bit crossings, async FIFOs, constraints, reset synchronisers and reset domain crossings.

25 design verification interview questions with answers: verification plans, coverage closure, testbench building blocks, UVM, and how to debug failing tests.

The RTL design interview questions that come up most, grouped by topic, with clear answers: coding style, FSMs, FIFOs, CDC, timing and resets.

30 SystemVerilog interview questions with answers and code: design features, classes and OOP, constraints, testbench mechanics, coverage and SVA.

26 Verilog interview questions with answers and code: blocking vs non-blocking, scheduling, latches, synthesis, and the modules interviewers ask you to write.

31 digital electronics interview questions with clear answers: number systems, Boolean logic, combinational and sequential circuits, timing and CMOS basics.

The Verilog coding guidelines I follow for synthesisable RTL: clocks, resets, combinational and sequential logic, synthesis rules, readability and lint.

The Verilog system tasks I actually use: $display vs $strobe vs $monitor, format specifiers, $finish, file I/O, $readmemh, waveform dumping, $random and $clog2.

How and when to use parameter, localparam and `define in Verilog, with examples, macro pitfalls, include guards, conditional compilation and other compiler directives.