The short answer: combinational logic produces outputs that depend only on the current inputs, with no memory and no clock. Adders, multiplexers, decoders, comparators and ALUs are all combinational. To design one, write down what each output should do, build a truth table, simplify it, implement it as gates or RTL, and verify every input combination.
Combinational logic is the first half of digital design; sequential logic, which adds memory, is the second. This guide is the starting point for the combinational topics on this site, and links to each one in more depth.
- Combinational vs sequential
- The design process
- A worked example: a 2-of-3 majority voter
- The common combinational blocks
- Pitfalls in real designs
Table of Contents
Part 1: Combinational vs sequential
| Combinational | Sequential | |
|---|---|---|
| Output depends on | Current inputs only | Inputs and stored state |
| Memory | None | Flip-flops or latches |
| Clock | Not needed | Usually needed |
| Examples | Adders, muxes, decoders | Counters, registers, FSMs |
Part 2: The design process
Part 3: A worked example: a 2-of-3 majority voter
Output F is 1 when at least two of the three inputs A, B and C are 1. From the truth table, F is 1 for inputs 011, 101, 110 and 111. Simplifying gives F = A·B + B·C + A·C. In Verilog:
module majority3 (
input wire a, b, c,
output wire f
);
assign f = (a & b) | (b & c) | (a & c);
endmoduleBecause there are only 8 input combinations, a testbench can check all of them, which is the safest way to verify small combinational blocks.
Part 4: The common combinational blocks
- Adders and subtractors
- Comparators, multipliers and the ALU
- Multiplexers and demultiplexers
- Encoders and decoders
Part 5: Pitfalls in real designs
- Unintended latches: in a combinational always block, assign every output in every path, or use defaults at the top.
- Glitches: outputs can briefly glitch as inputs change at different times. This is harmless when the output is sampled by a flop, but never use a combinational output as a clock or asynchronous reset.
- Long paths: deep logic limits clock frequency. Pipeline it if timing fails.
- Combinational loops: an output feeding back to its own input without a flop is almost always a bug.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
FAQ
Does combinational logic need a clock?
No. Outputs change whenever inputs change, after the gate delays.
How do I avoid latches in Verilog?
Use always @(*) (or always_comb), and assign every output in every branch, for example by setting defaults at the start of the block.
What is a glitch?
A short, unwanted pulse on an output caused by inputs changing at slightly different times. It matters only if the output is used asynchronously.
Why is exhaustive testing possible here?
Small combinational blocks have few enough input combinations to test them all, which proves the block correct.
