Setup and Hold Time in Flip-Flops: Explained with Examples

The short answer: setup time is how long a flip-flop’s input must be stable before the active clock edge; hold time is how long it must stay stable after it. If data arrives too late you get a setup violation, which you fix by making the path faster or slowing the clock. If data changes too soon after the edge you get a hold violation, which does not depend on clock frequency and is usually fixed by adding delay.

Setup and hold are the foundation of static timing analysis and one of the most asked interview topics. Here is a clear explanation with the equations you need.

1. The picture
2. The timing equations
3. Fixing setup violations
4. Fixing hold violations
5. Setup, hold and metastability

Part 1: The picture

Part 2: The timing equations

For a path from launching flop FF1 to capturing flop FF2, with clock period T and skew between their clocks:

Setup check:  T_clk2q + T_logic(max) + T_setup  <=  T + T_skew
Hold check:   T_clk2q + T_logic(min)            >=  T_hold + T_skew

T_skew = (clock arrival at FF2) - (clock arrival at FF1)

Notice that the clock period T appears in the setup equation but not in the hold equation. That is why slowing the clock fixes setup problems but never fixes hold problems.

Part 3: Fixing setup violations

• Reduce logic depth: restructure, or move logic before or after the flop (retiming).
• Add a pipeline stage to split a long path.
• Use faster (larger or low-Vt) cells, or improve placement to cut wire delay.
• As a last resort, lower the clock frequency.

Part 4: Fixing hold violations

• Add delay on the data path, usually buffers inserted during physical design.
• Reduce clock skew where the capture clock arrives late.
• Hold is checked at the fast corner, so fixes must be verified across corners.

Part 5: Setup, hold and metastability

If an input changes inside the setup-hold window, the flop can go metastable. Inside a synchronous design, STA prevents that. For signals from another clock domain, you cannot prevent it, so you use synchronisers instead. See clock domain crossing.

FAQ

Why doesn’t lowering the clock frequency fix hold violations?

Because the hold check compares the launch and capture of the same clock edge, so the clock period does not appear in it.

Can setup or hold time be negative?

Yes. Due to internal delays in the flip-flop, a library may specify a negative setup or hold time.

Which corner is worst for setup and for hold?

Setup is usually worst at the slow corner (slow process, low voltage, high or sometimes low temperature); hold at the fast corner.

What is slack?

The margin by which a timing check passes. Negative slack means a violation.