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RTL Design

FIFO Depth Calculation: A Simple Method with Worked Examples

Raju GorlaBy Raju Gorla9 September 2026Updated:11 October 2026No Comments4 Mins Read
FIFO depth calculation made simple
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The short answer: a FIFO must hold whatever the writer produces faster than the reader can drain it during the worst-case burst. So depth = burst length minus the number of words the reader can take out while that burst is being written. Work it out using rates in words per second, always for the worst-case burst, then add a small margin for latency such as pointer synchronisation in an asynchronous FIFO.

FIFO depth questions are a favourite in interviews because they test whether you can think about rates and time instead of memorising a formula. Here is the method I use, with three worked examples.

  1. The method
  2. Three worked examples
  3. Common mistakes
  4. What I would say in an interview

Table of Contents

  • Part 1: The method
  • Part 2: Three worked examples
    • Example 1: different clocks, no idle cycles
    • Example 2: idle cycles on the write side
    • Example 3: “80 words in any 100 cycles”
  • Part 3: Common mistakes
  • Part 4: What I would say in an interview
  • FAQ
    • What if the read rate is faster than the write rate?
    • Should FIFO depth be rounded to a power of two?
    • How much margin should I add?
    • Does the formula work for bursts that repeat?

Part 1: The method

  • Find the worst-case burst: the largest number of words the writer can push back to back.
  • Work out how long that burst takes to write: burst ÷ write rate (in words per second, after accounting for idle cycles).
  • Work out how many words the reader removes in that time: time × read rate.
  • Depth = burst − words read. Round up, and add margin for latency.
Depth = B - (B / R_write) * R_read

B       = worst-case burst length (words)
R_write = effective write rate (words per second)
R_read  = effective read rate (words per second)

Part 2: Three worked examples

Three worked FIFO depth calculation examples
The same method works for all three.

Example 1: different clocks, no idle cycles

Write clock 100 MHz, read clock 50 MHz, burst of 80 words written every cycle and read every cycle. The burst takes 80 ÷ 100 MHz = 800 ns. In 800 ns the reader takes 800 ns × 50 MHz = 40 words. Depth = 80 − 40 = 40.

Example 2: idle cycles on the write side

Write clock 100 MHz but only one write every 2 cycles (50 million words per second), read clock 40 MHz with a read every cycle, burst of 160 words. The burst takes 160 ÷ 50 M = 3.2 µs; the reader takes 3.2 µs × 40 M = 128 words. Depth = 160 − 128 = 32.

Example 3: “80 words in any 100 cycles”

Write clock 100 MHz; the writer sends 80 words in any window of 100 cycles, with the idle cycles placed anywhere. Reader at 80 MHz, one word per cycle. The worst case is 80 words at the end of one window and 80 at the start of the next: 160 back to back. They take 1.6 µs; the reader takes 1.6 µs × 80 M = 128 words. Depth = 160 − 128 = 32.

Part 3: Common mistakes

  • Using clock frequencies instead of actual data rates when there are idle cycles.
  • Forgetting the back-to-back worst case at window boundaries (Example 3).
  • Ignoring read latency: if the reader starts a few cycles late, those words also need space.
  • In asynchronous FIFOs, ignoring the few cycles of pointer synchronisation delay before full and empty update.
  • Forgetting that if the average write rate is higher than the read rate, no finite depth is enough.

Part 4: What I would say in an interview

Talk through the method out loud: “worst-case burst, time to write it, words drained in that time, the difference, plus margin”. Interviewers care more about the reasoning than the number, and saying the assumptions out loud (are reads continuous? does the reader start immediately?) shows you understand the real design.

Practise this on VLSI Forge

I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.

FIFO design problems · CDC and RDC problems

FAQ

What if the read rate is faster than the write rate?

Then the FIFO never fills during steady traffic, and the minimum depth is set by latency and handshaking, often just a few entries.

Should FIFO depth be rounded to a power of two?

For asynchronous FIFOs, almost always, because of Gray-code pointers. For synchronous FIFOs it is convenient but not required.

How much margin should I add?

Typically a few entries for read latency and, in async FIFOs, synchronisation delay. The exact number depends on the design.

Does the formula work for bursts that repeat?

Only if the average write rate over a long time is not higher than the read rate. Otherwise the FIFO will eventually overflow no matter how deep it is.

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Previous ArticleSynchronous FIFO Design in Verilog: Pointers, Full and Empty
Next Article Reset Domain Crossing (RDC) and Reset Synchronisers Explained
Raju Gorla
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