The short answer: in a Moore machine the outputs depend only on the current state; in a Mealy machine they depend on the current state and the inputs. Mealy machines often need fewer states and react one cycle earlier, but their outputs can change (and glitch) whenever the inputs do, so they are often registered. Moore outputs are stable for a whole clock cycle and easier to time.
FSMs are the most common RTL interview topic, and a core skill for control logic. This post combines my older Mealy, Moore and Mealy-vs-Moore posts, with a complete Verilog template.
- The same problem, two ways
- Mealy vs Moore compared
- A clean FSM template in Verilog
- State encoding
- Tips I would follow
Table of Contents
Part 1: The same problem, two ways
Part 2: Mealy vs Moore compared
| Moore | Mealy | |
|---|---|---|
| Output depends on | State only | State and inputs |
| Number of states | Often more | Often fewer |
| Output timing | One cycle after the input | Same cycle as the input |
| Glitches on outputs | No (from flops) | Possible, if inputs glitch |
| Typical use | Control outputs that must be stable | Fast responses, then registered |
Part 3: A clean FSM template in Verilog
I always write FSMs in two (or three) blocks: one clocked block for the state register, one combinational block for next state and outputs. This is the Moore version of the detector above:
module detect11_moore (
input wire clk, rst_n, in,
output wire det
);
localparam S0 = 2'd0, S1 = 2'd1, S2 = 2'd2;
reg [1:0] state, next;
always @(posedge clk or negedge rst_n)
if (!rst_n) state <= S0;
else state <= next;
always @(*) begin
next = state; // default avoids latches
case (state)
S0: next = in ? S1 : S0;
S1: next = in ? S2 : S0;
S2: next = in ? S2 : S0;
default: next = S0;
endcase
end
assign det = (state == S2); // Moore: output from state only
endmoduleThe Mealy version needs only S0 and S1, and its output is det = (state == S1) && in.
Part 4: State encoding
- Binary: fewest flops. Good for ASICs with many states.
- One-hot: one flop per state; very simple next-state logic. Popular on FPGAs.
- Gray: only one bit changes per transition in sequential FSMs, which can reduce power and glitches.
- Synthesis tools can re-encode FSMs automatically if you let them.
Part 5: Tips I would follow
- Always include a default in case statements and a safe reset state.
- Keep outputs registered when they drive other blocks or I/O.
- Draw the state diagram before writing any code.
- For interviews, practise sequence detectors (overlapping and non-overlapping), traffic lights and vending machines.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
FSM problems · Daily challenge
FAQ
Which is better, Mealy or Moore?
Neither always. Moore is simpler to time and has stable outputs; Mealy can be smaller and faster to respond. Many designs use Moore, or Mealy with registered outputs.
What is the difference between overlapping and non-overlapping sequence detection?
Overlapping detection lets the end of one match be the start of the next (1011011 contains two 1011s); non-overlapping restarts after each match.
Why use one-hot encoding?
Next-state logic is very simple, which helps speed, especially on FPGAs where flops are plentiful.
How do I avoid latches in FSM code?
Assign a default to next and to every output at the top of the combinational block.
