How advanced nodes changed physical design: FinFET and gate-all-around transistors, wire resistance, backside power, EUV and multi-patterning, chiplets and 3D ICs, and PD for AI chips.
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What happens at tape-out: the sign-off checklist, GDSII/OASIS stream-out, mask data preparation with OPC and fracturing, full masks vs MPW, metal ECOs and first silicon.
How physical design optimises power and area: leakage and dynamic power in P&R, area recovery, multiple voltage domains, power gating with switches, isolation and retention, and measuring PPA.
Physical verification explained: DRC, LVS, ERC, the antenna effect and its fixes, density and fill, DFM and mask rule checks, and how to run sign-off verification.
Power integrity and reliability explained: static and dynamic IR drop, how IR drop affects timing, power and signal electromigration, and how to fix both.
Sign-off STA explained: process, voltage, temperature and RC corners, modes and scenarios, keeping MCMM manageable, OCV, CRPR and PBA, and sign-off criteria.
Timing closure in physical design: reading WNS and TNS, diagnosing failing paths, fixing setup and hold violations, timing, functional and metal-only ECOs, and habits for faster closure.
Wire parasitics and crosstalk explained: resistance and capacitance, extraction and SPEF, coupling capacitance, delta delay, noise glitches, timing windows and how to fix crosstalk.
Routing explained: global routing, track assignment, detailed routing, routing algorithms, metal layers, vias and redundant vias, special nets and post-route steps.
Clock tree synthesis explained: CTS goals and constraints, skew, latency and jitter, useful skew, tree, H-tree and mesh structures, clock gating and post-CTS steps.