The short answer: Sign-off STA checks timing in a dedicated sign-off tool, with extracted parasitics, across every combination of mode and corner (MCMM): process, voltage, temperature and RC corners crossed with functional, test and low-power modes. It includes on-chip variation (derates, AOCV or POCV), crosstalk and clock reconvergence pessimism removal. A block is signed off when every scenario meets setup, hold, transition, capacitance and other checks with the agreed margins.
Place-and-route tools have their own timing engines, but the final answer comes from a sign-off STA tool such as PrimeTime or Tempus, run on the extracted design. This post explains what that run covers and how teams keep it manageable. It combines my older posts on sign-off STA and multi-corner multi-mode analysis.
For STA fundamentals (setup, hold, SDC), see my STA interview questions.
- What has to be covered
- Corners, modes and scenarios
- Keeping MCMM manageable
- Variation and pessimism
- Sign-off criteria
Table of Contents
Part 1: What has to be covered
Part 2: Corners, modes and scenarios
A corner is a set of conditions: a library characterisation (process, voltage, temperature) plus an RC extraction corner. A mode is a set of constraints: which clocks run, at what frequency, and which case-analysis settings apply. A scenario is one mode at one corner.
| Typical check | Usually worst at |
|---|---|
| Setup | Slow process, low voltage, and the RC corner with most delay (temperature depends on the node) |
| Hold | Fast process, high voltage, and the RC corner with least delay |
| Max transition / capacitance | Slow corners |
| Leakage power | Fast process, high temperature |
At advanced nodes, temperature inversion means low temperature can be the slowest corner, so both temperature extremes are checked.
Part 3: Keeping MCMM manageable
- A full matrix can be dozens of scenarios. Teams analyse all of them at sign-off but optimise in P&R on a dominant subset that covers the worst cases.
- Merge or prune scenarios that are always dominated by others.
- Use consistent SDC per mode across P&R and sign-off to avoid correlation surprises.
- Track correlation between the P&R timer and the sign-off timer; large gaps mean different settings or parasitics.
Part 4: Variation and pessimism
On-chip variation is modelled with derates (flat), AOCV (depth- and distance-based) or POCV/LVF (statistical, per cell). CRPR removes the impossible pessimism on the shared part of launch and capture clock paths. Path-based analysis (PBA) recalculates critical paths with their real slews to recover pessimism from graph-based analysis.
Part 5: Sign-off criteria
- No setup or hold violations in any scenario (or only waived ones with sign-off from the owners).
- No max transition, capacitance or fan-out violations.
- Clock checks: gating, pulse width, minimum period.
- Noise and crosstalk checks clean.
- Constraints reviewed: no unconstrained paths, exceptions justified.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Previous in my physical design series: Timing closure and ECOs. Next: IR drop and electromigration.
FAQ
What is MCMM?
Multi-corner multi-mode analysis: checking timing in every combination of operating mode and process, voltage, temperature and RC corner.
What is the difference between a corner and a mode?
A corner sets physical conditions (process, voltage, temperature, RC); a mode sets the constraints (clocks, frequencies, test or functional configuration).
Why does sign-off use a different tool from P&R?
Sign-off tools are the reference, with detailed SI and variation analysis on extracted parasitics. P&R timers approximate them for speed during optimisation.
What is temperature inversion?
At low supply voltages in advanced nodes, transistors can be slower when cold, so the low-temperature corner may be the worst for setup.
