x86, Arm and RISC-V explained simply: what an ISA is, how the three differ, where each is used, and what it means for VLSI engineers.
Author: Raju Gorla
17 Tcl interview questions for VLSI engineers with answers and scripts: substitution and quoting, lists and dicts, upvar, regexp, file handling, collections in EDA tools and report parsing.
How PD engineers use Tcl: querying cells and nets, timing reports, scripted floorplans, structuring a P&R flow, and good scripting habits.
How advanced nodes changed physical design: FinFET and gate-all-around transistors, wire resistance, backside power, EUV and multi-patterning, chiplets and 3D ICs, and PD for AI chips.
What happens at tape-out: the sign-off checklist, GDSII/OASIS stream-out, mask data preparation with OPC and fracturing, full masks vs MPW, metal ECOs and first silicon.
How physical design optimises power and area: leakage and dynamic power in P&R, area recovery, multiple voltage domains, power gating with switches, isolation and retention, and measuring PPA.
Physical verification explained: DRC, LVS, ERC, the antenna effect and its fixes, density and fill, DFM and mask rule checks, and how to run sign-off verification.
Power integrity and reliability explained: static and dynamic IR drop, how IR drop affects timing, power and signal electromigration, and how to fix both.
Sign-off STA explained: process, voltage, temperature and RC corners, modes and scenarios, keeping MCMM manageable, OCV, CRPR and PBA, and sign-off criteria.
Timing closure in physical design: reading WNS and TNS, diagnosing failing paths, fixing setup and hold violations, timing, functional and metal-only ECOs, and habits for faster closure.