The short answer: Clock tree synthesis (CTS) builds the network of buffers or inverters and wires that carries each clock from its source to every flip-flop, memory and clock gate. Its goals are low skew (similar arrival times at related flops), controlled insertion delay (latency), clean transitions and low power, while respecting max transition, capacitance and fan-out limits. Common structures are balanced trees, H-trees, meshes and multi-source CTS. After CTS, timing uses real (propagated) clocks, and hold violations are fixed.
The clock network switches every cycle and reaches every register, so it’s often a large share of a chip’s dynamic power and has a direct effect on timing. This post combines my older posts on CTS, clock tree structures, skew, jitter and latency, and clock gating.
- The picture
- CTS goals and constraints
- Skew, latency and jitter
- Clock tree structures
- Clock gating and CTS
- After CTS
Table of Contents
Part 1: The picture
Part 2: CTS goals and constraints
| Target | Why it matters |
|---|---|
| Skew | Uncontrolled skew eats setup or hold margin |
| Latency (insertion delay) | Long latency increases on-chip variation effects |
| Transition | Slow clock edges add delay and power, and worsen variation |
| Power | Fewer, well-sized buffers and shorter wires |
| Design rules | Max transition, capacitance and fan-out on clock nets |
CTS is guided by a specification: target skew and latency per clock, which buffers and inverters to use, non-default routing rules (wider spacing, shielding) for clock nets, and which pins are sinks or should be ignored.
Part 3: Skew, latency and jitter
- Latency is the delay from the clock source to a flop’s clock pin: source latency (outside the block or before the root) plus network latency (the tree).
- Skew is the difference in latency between two flops. What matters is skew between flops that talk to each other (local skew), not global skew.
- Jitter is variation of the clock edge itself, from the PLL and supply noise. CTS can’t remove it; STA covers it with clock uncertainty.
- Useful skew: deliberately delaying a capture clock to borrow time for a critical path. Modern tools do this as part of CTS optimisation (concurrent clock and data optimisation).
Part 4: Clock tree structures
| Structure | Strengths | Costs |
|---|---|---|
| Balanced tree (buffered) | Flexible, low power, standard flow | Higher skew sensitivity to variation |
| H-tree | Very balanced by construction | Rigid, needs symmetric placement |
| Clock mesh | Very low skew, robust to variation | High power and routing; used in high-performance CPUs |
| Multi-source CTS / spine | Low skew over large areas with less power than a mesh | More complex setup |
Part 5: Clock gating and CTS
Integrated clock gating cells, inserted during synthesis, stop the clock to idle registers. CTS treats them as part of the tree: it places them near their flops, balances the gated and ungated branches, and checks the clock gating setup and hold timing on the enable. Gating high in the tree saves the most power, because the whole sub-tree stops toggling.
Part 6: After CTS
- Switch STA from ideal to propagated clocks.
- Fix hold violations: they show up now, because real skew exists.
- Check clock transitions and the clock tree report for unbalanced or overloaded branches.
- Re-run timing optimisation; data paths may need resizing for the real clock arrival times.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Physical Design problems · Static Timing Analysis problems
Previous in my physical design series: Placement. Next: Routing.
FAQ
What is clock tree synthesis?
The physical design step that builds the buffered network distributing each clock to all its sinks with controlled skew, latency, transition and power.
What is the difference between skew and jitter?
Skew is a spatial difference in arrival time between flops; jitter is temporal variation of the clock edge itself.
Why are hold violations fixed after CTS?
Because real clock skew only exists once the tree is built; before CTS, clocks are ideal.
What is a clock mesh?
A grid of wires driven by many buffers that shorts the clock network together, giving very low skew at the cost of power and routing.
