What Is SystemVerilog? Features for Design and Verification

The short answer: SystemVerilog (IEEE 1800) is the successor to Verilog. It keeps everything in Verilog and adds two big groups of features: better constructs for RTL design (logic, always_ff and always_comb, enums, structs, interfaces, packages) and a complete object-oriented verification language (classes, constrained randomisation, functional coverage, assertions, DPI). It’s the language behind UVM and is used in almost every modern ASIC flow.

If you already know Verilog, SystemVerilog will feel familiar on day one: every Verilog file is also valid SystemVerilog. The difference is how much more it lets you say, especially when you build testbenches.

This is the first post in my SystemVerilog series, which follows on from my Verilog series.

1. Verilog plus two sets of features
2. A short history
3. What changes for RTL designers
4. What changes for verification
5. Do you need to learn it?
6. Tools
7. This series in order

Part 1: Verilog plus two sets of features

Part 2: A short history

• SystemVerilog began as an extension of Verilog in the early 2000s, combining ideas from several verification languages.
• It became IEEE 1364’s successor as IEEE 1800-2005, and Verilog was merged into it in IEEE 1800-2009.
• The latest revision is IEEE 1800-2023. Today, “SystemVerilog” is simply the standard HDL for most ASIC teams.

Part 3: What changes for RTL designers

module counter #(parameter int W = 8) (
  input  logic         clk, rst_n, en,
  output logic [W-1:0] count
);
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n)  count <= '0;
    else if (en) count <= count + 1'b1;
endmodule

• logic replaces the wire vs reg question.
• always_ff and always_comb say what you mean, and tools check it.
• '0 fills any width with zeros.
• Enums, structs and interfaces make designs shorter and safer. See SystemVerilog for RTL design.

Part 4: What changes for verification

class packet;
  rand bit [7:0] len;
  rand bit [7:0] data[];
  constraint c_len  { len inside {[1:64]}; }
  constraint c_data { data.size() == len; }
endclass

initial begin
  packet p;
  p = new();
  repeat (100) begin
    assert (p.randomize());
    drive(p);
  end
end

Classes, randomisation, coverage and assertions turn the testbench into real software. That’s what made constrained-random, coverage-driven verification, and later UVM, possible.

Part 5: Do you need to learn it?

Part 6: Tools

Commercial simulators (Questa, VCS, Xcelium) support the full language. Free options are improving: Verilator supports a large and growing part of SystemVerilog, and Icarus Verilog supports parts of it. VLSI Forge also accepts SystemVerilog on its problems.

Part 7: This series in order

1. What is SystemVerilog?
2. SystemVerilog data types
3. SystemVerilog for RTL design
4. Tasks and functions
5. Interfaces, modports and clocking blocks
6. Classes and OOP
7. Constrained randomisation
8. Threads and inter-process communication
9. SystemVerilog assertions
10. Functional coverage
11. Testbench architecture
12. DPI
13. Design patterns

Next: SystemVerilog data types.

FAQ

What is the difference between Verilog and SystemVerilog?

SystemVerilog is a superset of Verilog. It adds better design constructs and a full object-oriented verification language with randomisation, coverage and assertions.

Is SystemVerilog synthesisable?

The design subset is: logic, always_ff, always_comb, enums, structs, interfaces, packages and so on. Classes and randomisation are for testbenches only.

Should I learn Verilog before SystemVerilog?

It helps, because SystemVerilog builds on Verilog. But you can learn the synthesisable core directly in SystemVerilog style.

Is UVM part of SystemVerilog?

No. UVM is a class library written in SystemVerilog, standardised separately as IEEE 1800.2.