Browsing: HDL programming

Verilog

Blocking vs Non-Blocking Assignments in Verilog (with Waveforms)

Raju Gorla25 July 2026

Blocking (=) vs non-blocking (<=) assignments explained with waveforms, the Verilog scheduling regions behind them, race conditions, and the rules to follow in RTL.

System Verilog

Functional Coverage in SystemVerilog: Covergroups, Bins and Crosses

Raju Gorla13 July 2026

How to write functional coverage in SystemVerilog: covergroups, coverpoints, bins, crosses, transition coverage, cover properties, where to sample and how to close coverage.

System Verilog

What Is SystemVerilog? Features for Design and Verification

Raju Gorla4 July 2026

What SystemVerilog is, how it extends Verilog for RTL design and verification, a short history, what each role needs to learn, and a learning path.