The Verilog system tasks I actually use: $display vs $strobe vs $monitor, format specifiers, $finish, file I/O, $readmemh, waveform dumping, $random and $clog2.
Browsing: FPGA Programming
How and when to use parameter, localparam and `define in Verilog, with examples, macro pitfalls, include guards, conditional compilation and other compiler directives.
How to write combinational logic in Verilog: a five-step checklist, ALU, priority encoder, decoder and mux examples, avoiding latches and loops, and thinking about timing.
What SystemVerilog is, how it extends Verilog for RTL design and verification, a short history, what each role needs to learn, and a learning path.