Browsing: Digital Design

The Verilog system tasks I actually use: $display vs $strobe vs $monitor, format specifiers, $finish, file I/O, $readmemh, waveform dumping, $random and $clog2.

Verilog templates for flip-flops (async and sync reset, enable), latches, registers, shift registers, pipelines and counters, with rules for sequential blocks.

What SystemVerilog is, how it extends Verilog for RTL design and verification, a short history, what each role needs to learn, and a learning path.