The short answer: VHDL interviews test whether you understand its simulation model and its strict typing: entities and architectures, signals vs variables and delta cycles, processes and sensitivity lists, std_logic and numeric_std, rising_edge, latch inference, generics and generate, and how to write synthesisable registers, counters and FSMs. VHDL is common in Europe, defence, aerospace and FPGA teams, so expect it there more than in ASIC product companies.
Most VLSI jobs in India and the US use Verilog and SystemVerilog, but VHDL is still widely used in FPGA, defence, aerospace and many European companies. If the job description mentions VHDL, expect the interviewer to check that you really know it, not just that you can read it.
If you also use Verilog, my Verilog interview questions cover the same concepts from the other side.
- Structure and simulation model
- Types
- Writing synthesisable VHDL
- Testbenches and VHDL-2008
Table of Contents
Part 1: Structure and simulation model
1. What are an entity and an architecture?
The entity declares the interface: ports and generics. The architecture describes the behaviour or structure behind it. One entity can have several architectures (say, an RTL one and a behavioural model), and a configuration, or the last compiled architecture, decides which is used.
2. What is the difference between a signal and a variable?
A signal assignment (<=) is scheduled and takes effect after the current delta cycle, so inside a process you still read the old value. A variable assignment (:=) takes effect immediately and is local to the process. In synthesis, a variable read before it’s written in a clocked process becomes a register; one written before it’s read becomes plain logic.
3. What is a delta cycle?
An infinitely small step of simulation time. When signals change, processes sensitive to them run, possibly changing more signals, and each round is a delta cycle at the same simulation time. It lets VHDL model concurrent hardware deterministically.
4. What happens if a signal is missing from a process sensitivity list?
In simulation, the process won’t re-run when that signal changes, so the output looks like a latch. Synthesis ignores the list and builds combinational logic, so simulation and hardware disagree. VHDL-2008’s process(all) avoids this.
5. What is the difference between concurrent and sequential statements?
Concurrent statements (signal assignments, when-else, with-select, component instances, processes themselves) sit in the architecture and all run in parallel. Sequential statements (if, case, loops, variable assignments) run in order inside a process, function or procedure.
6. What is the difference between inertial and transport delay?
Inertial delay, the default, filters out pulses shorter than the delay, like a real gate. Transport delay passes every pulse, like an ideal wire. Both are for simulation only; synthesis ignores delays.
Part 2: Types
7. What is the difference between bit, std_ulogic and std_logic?
bit has only 0 and 1. std_ulogic has nine values: U, X, 0, 1, Z, W, L, H and ‘-’. std_logic is the resolved subtype of std_ulogic, so a signal can have multiple drivers (like a tri-state bus) with a resolution function deciding the result. Most designs use std_logic everywhere.
8. Why use numeric_std instead of std_logic_arith?
numeric_std is the IEEE standard package and defines signed and unsigned types with clear arithmetic. std_logic_arith and std_logic_unsigned were vendor packages that are not standard and can conflict. Good practice is numeric_std only.
9. Why do I need so many type conversions in VHDL?
VHDL is strongly typed: std_logic_vector, unsigned, signed and integer are all different types. That catches many bugs at compile time, but means converting explicitly:
signal a : std_logic_vector(7 downto 0);
signal u : unsigned(7 downto 0);
signal n : integer range 0 to 255;
u <= unsigned(a); -- type cast, same width
n <= to_integer(u);
a <= std_logic_vector(to_unsigned(n, 8));10. Why should integers have a range?
An unconstrained integer is at least 32 bits, so synthesis may build 32-bit logic. integer range 0 to 15 tells the tool it only needs four bits.
11. What are the most useful attributes?
‘event, ‘range, ‘length, ‘high, ‘low, ‘left and ‘right. ‘range and ‘length let you write code that adapts to the width of a port, which keeps modules generic.
Part 3: Writing synthesisable VHDL
12. rising_edge(clk) or clk’event and clk = ‘1’?
rising_edge(clk) only returns true for a real 0 to 1 transition (including L to H), while clk’event and clk = ‘1’ is also true for X to 1. In practice both synthesise to the same flop, but rising_edge is clearer and safer in simulation, so I use it.
13. Write a D flip-flop with asynchronous reset.
process (clk, rst_n)
begin
if rst_n = '0' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;14. Write a 4-bit counter with enable.
signal count : unsigned(3 downto 0);
...
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
count <= (others => '0');
elsif en = '1' then
count <= count + 1;
end if;
end if;
end process;
count_out <= std_logic_vector(count);15. When is a latch inferred in VHDL?
When a combinational process doesn’t assign an output in every path, for example an if without an else. Assign default values at the start of the process, or cover every case with others.
16. How do you write an FSM in VHDL?
Declare an enumerated type for the states, use one clocked process for the state register and one combinational process (or a case inside the clocked process) for next state and outputs. Enumerated types let the synthesis tool choose the encoding and make waveforms readable.
17. What are generics and generate statements for?
Generics are parameters of an entity, such as a data width or depth, set at instantiation. for-generate replicates hardware, and if-generate includes it conditionally, both at elaboration time.
18. What is the difference between a function and a procedure?
A function returns a single value, can’t contain wait statements, and is used in expressions. A procedure can have several outputs through out parameters and, in testbenches, can contain waits.
Part 4: Testbenches and VHDL-2008
19. How do you generate a clock and check results in a VHDL testbench?
clk <= not clk after 5 ns; -- concurrent clock, 10 ns period
stim : process
begin
rst <= '1';
wait for 20 ns;
rst <= '0';
wait until rising_edge(clk);
assert count_out = x"0"
report "count should be 0 after reset" severity error;
wait;
end process;20. What did VHDL-2008 add that interviewers ask about?
- process(all) for complete sensitivity lists.
- Reading out ports inside the architecture.
- The ?? condition operator and simpler conditional expressions.
- Fixed-point and floating-point packages.
- Unconstrained elements in arrays and records, and better generics.
21. How does VHDL compare with Verilog?
| VHDL | Verilog | |
|---|---|---|
| Typing | Strong, explicit conversions | Weak, implicit conversions |
| Verbosity | More verbose | More compact |
| Simulation model | Delta cycles, signals vs variables | Event regions, blocking vs non-blocking |
| Common in | FPGA, defence, aerospace, Europe | ASIC product companies, most of India and the US |
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FAQ
Should I learn VHDL or Verilog first?
Learn the one your target jobs use. For most ASIC jobs that’s Verilog and SystemVerilog. For FPGA, defence and many European roles, VHDL is still common. The hardware concepts are the same.
Is VHDL still used?
Yes, especially in FPGA design, aerospace, defence, rail and many European companies. Mixed-language designs are also common.
What is the most common VHDL interview question?
Signal vs variable, closely followed by why a missing sensitivity list causes a simulation-synthesis mismatch.
Do I need VHDL-2008?
It’s widely supported now and makes code cleaner. Know its main features, but be ready to work in VHDL-93 style on older projects.
