DDR Interview Questions: DRAM Timing, Controllers and PHY Training

The short answer: DDR interviews cover how DRAM is organised (channels, ranks, bank groups, banks, rows, columns), the basic commands and timings (ACT, READ, WRITE, PRE, refresh; tRCD, CL, tRP, tRAS, tFAW), what changed from DDR4 to DDR5, how a memory controller schedules requests, and how the PHY captures data with strobes and training. Verification roles add memory models, protocol checkers and training coverage.

Almost every SoC has a DDR or LPDDR interface, so memory questions come up for controller designers, PHY engineers, verification engineers and SoC architects. The trick is to understand why DRAM behaves the way it does; once you do, the timing parameters make sense on their own.

The picture below is the one I’d draw first in any DDR interview.

1. DRAM basics
2. DDR generations
3. The memory controller
4. The PHY and training
5. Verification

Part 1: DRAM basics

1. What does “double data rate” mean?

Data is transferred on both the rising and falling edges of the strobe, so a 1600 MHz clock gives 3200 MT/s (mega-transfers per second).

2. How is DRAM organised?

A channel contains one or more ranks (sets of chips that share the bus and respond together). Each chip has bank groups, each bank group has banks, and each bank is an array of rows and columns. An address is split into bank group, bank, row and column bits by the controller.

3. Why does DRAM need ACTIVATE and PRECHARGE?

A DRAM cell is a tiny capacitor. ACTIVATE copies a whole row into the bank’s sense amplifiers (the “row buffer”); reads and writes then use columns of that open row. PRECHARGE writes the row back and prepares the bank for a different row. Accessing an already-open row (a row hit) is much faster than opening a new one.

4. Why does DRAM need refresh?

The cell capacitors leak, so every row must be refreshed periodically, typically within a 64 ms window at normal temperature, with the interval halved at high temperature. The controller issues REFRESH commands at an average interval (tREFI); during tRFC the affected banks can’t be used, which costs bandwidth.

5. Explain the main DRAM timing parameters.

6. Why are there short and long timings for bank groups?

Banks in the same bank group share some internal circuitry, so back-to-back accesses within a group need more time (the _L timings) than accesses that alternate between groups (_S). Controllers interleave across bank groups to keep the bus busy.

Part 2: DDR generations

7. What changed from DDR4 to DDR5?

Note that DDR5 on-die ECC protects the cells inside the chip; it doesn’t replace system-level ECC on the bus.

8. How are LPDDR and HBM different from DDR?

LPDDR is designed for mobile power: lower voltages, deep power-down states, and point-to-point connections to the SoC. HBM stacks DRAM dies with through-silicon vias and connects them to the SoC over a very wide interface on an interposer, giving huge bandwidth per watt, which is why AI accelerators use it.

9. What is the prefetch architecture?

The DRAM core runs much slower than the I/O. Each access fetches several bits per data pin at once (8n in DDR4, 16n in DDR5) and serialises them onto the bus as a burst. That’s why burst length grows with each generation.

Part 3: The memory controller

10. What does a DDR memory controller do?

It turns read and write requests from the SoC into legal DRAM commands: mapping addresses to banks and rows, scheduling commands within all the timing rules, issuing refreshes, managing power-down and self-refresh, and often adding ECC. It connects to the PHY, usually through the DFI interface.

11. Open-page or closed-page policy?

Open page leaves a row open after an access, betting that the next access hits the same row: great for sequential traffic. Closed page precharges right away, which helps random traffic because the next access doesn’t first need a precharge. Many controllers use adaptive policies.

12. How do controllers schedule requests?

A common approach is FR-FCFS (first-ready, first-come-first-served): serve row hits first, then the oldest request. Controllers also batch writes to reduce read-write turnaround, interleave across banks and bank groups, and add QoS so latency-sensitive masters (like a display controller) aren’t starved.

13. Why does address mapping matter?

Which address bits select the bank, row and column decides how evenly traffic spreads. A good mapping puts consecutive cache lines in different banks or bank groups so they can be accessed in parallel. Many controllers XOR row bits into bank bits to avoid conflicts.

14. What is row hammer, and how is it mitigated?

Activating a row many times quickly can flip bits in neighbouring rows. Mitigations include target row refresh in the DRAM, refresh management commands in DDR5, controller-side activation counters, and ECC.

Part 4: The PHY and training

15. What is DQS, and how is data captured?

DQS is a strobe sent with the data (source-synchronous). On reads, the DRAM sends DQS edge-aligned with the data, and the PHY delays it by about a quarter cycle to sample in the middle of the data eye. On writes, the controller sends DQS centre-aligned with the data.

16. Why is training needed?

At these speeds, board traces, packages and process variation shift the timing of every signal differently. Training finds the right delays and voltages at power-up instead of relying on fixed values.

17. What are the main training steps?

• ZQ calibration: set driver strength and termination against a precise resistor.
• Write leveling: align DQS to the clock at each DRAM, needed because of the fly-by clock routing on DIMMs.
• Read gate training: find when to start listening for the read strobe.
• Read and write eye centring: centre the sampling point for each DQ bit.
• Vref training: set the reference voltage for the receivers.
• CA training (DDR5 and LPDDR): align the command and address bus.

18. What is ODT?

On-die termination: the DRAM switches termination resistors on its data pins when needed, reducing reflections without external resistors. The controller (or mode registers) decides which rank terminates during each access.

19. What are mode registers?

Configuration registers inside the DRAM that set CAS latency, burst length, ODT values, drive strength and other options. The controller programs them with MRS (or MRW) commands during initialisation.

Part 5: Verification

20. How would you verify a DDR controller?

• Connect a memory model from a VIP vendor or the DRAM supplier that checks every timing parameter.
• Build a scoreboard that checks read data against what was written.
• Cover row hits, misses and conflicts, every bank and bank group, refresh during traffic, power-down and self-refresh entry and exit.
• Run with several timing configurations and speed bins, and include ECC error injection if ECC is supported.

21. Why is a memory controller hard to verify?

The number of timing rules is large, the scheduler reorders requests, and the interesting bugs happen only with specific mixes of traffic, refresh and power events. Constrained-random traffic with good coverage of scheduling corner cases is essential.

FAQ

Do I need to memorise DDR timing values?

No. Know what each parameter means and why it exists. Real values come from the datasheet for each speed bin.

Which roles get DDR questions?

Memory controller and PHY designers, verification engineers on memory subsystems, SoC architects and, for training and timing, some STA and signal integrity roles.

Should I learn DDR4 or DDR5?

Learn the basics on DDR4, which has simpler documentation, then learn what DDR5 changed. Interviewers often ask exactly that comparison.

What is the most common DDR interview question?

Explaining ACT, READ and PRE with tRCD, CL and tRP, followed by “why does DRAM need refresh?”