The short answer: synthesis interviews check whether you understand how RTL becomes gates: the inputs (RTL, Liberty libraries, SDC constraints) and outputs (netlist, constraints, reports), what the tool does in each step, how coding style affects the result, and how you judge and improve quality of results (timing, area, power). Expect questions on simulation-synthesis mismatches, clock gating, multi-Vt cells, hierarchy, and equivalence checking.
Synthesis sits right between the RTL and physical design teams, so these questions come up for RTL designers, synthesis engineers and PD engineers alike. Interviewers aren’t looking for tool commands; they want to know you can read a timing or area report and explain what the tool did with your code.
For the language side of synthesis (latches, blocking vs non-blocking), see my Verilog interview questions too.
- The synthesis flow
- Coding style and the netlist
- Optimisation and power
- Checking the results
Table of Contents
Part 1: The synthesis flow
1. What is logic synthesis?
Converting RTL into a gate-level netlist of standard cells from a target library, while meeting timing, area and power goals. It has three parts: translation into generic logic, optimisation, and mapping onto real library cells.
2. What are the inputs and outputs of synthesis?
Inputs: the RTL, Liberty (.lib or .db) timing libraries, SDC constraints, and often physical data (LEF, technology files, a floorplan) for physical-aware synthesis, plus UPF for low-power designs. Outputs: the netlist, updated SDC, and reports on timing, area, power and QoR. Teams then run equivalence checking on the netlist.
3. What happens during elaboration?
The tool resolves parameters and generate blocks, builds the design hierarchy, and infers registers, latches, muxes and operators from the RTL. Many coding problems, like inferred latches or multiple drivers, show up as elaboration warnings, so I always read them.
4. Why did physical-aware synthesis replace wire load models?
Wire load models estimated wire capacitance from fan-out and block size, which became very inaccurate at small nodes where wires dominate delay. Physical-aware synthesis (for example Fusion Compiler or Genus with iSpatial-style flows) places cells roughly while synthesising, so its timing correlates much better with place and route.
Part 2: Coding style and the netlist
5. What causes simulation-synthesis mismatches?
- Incomplete sensitivity lists (use always @(*) or always_comb).
- Delays (#) and initial blocks, which synthesis ignores.
- full_case and parallel_case pragmas, which change synthesis but not simulation.
- casex and x-assignments, which simulate optimistically.
- Blocking assignments in sequential logic, creating races in simulation.
6. When does synthesis infer a latch?
When a combinational block doesn’t assign a variable in every path. Latches are hard to time and to test, so unintended ones are bugs. Reading the elaboration report for inferred latches should be part of every synthesis run.
7. How are for loops synthesised?
They’re unrolled at elaboration into parallel hardware, so the bounds must be static. A loop over 32 bits that adds produces an adder tree, not a sequential loop.
8. What is resource sharing?
If two operations are never needed at the same time (for example, a + b in one branch of an if and c + d in the other), the tool can use one adder with muxes on its inputs. It saves area but adds mux delay, so tools only do it when timing allows.
9. How does the tool choose adder or multiplier architectures?
Synthesis tools have datapath libraries (DesignWare in Synopsys tools, for example) with several implementations of each operator: ripple, carry-lookahead, parallel-prefix and so on. The tool picks the smallest one that meets timing.
10. What is retiming?
Moving registers across combinational logic to balance the delay between pipeline stages, without changing the function seen at the outputs. It can fix timing without RTL changes, but makes the netlist harder to compare with the RTL, and equivalence checking needs to be told about it.
Part 3: Optimisation and power
11. What is the usual priority of synthesis goals?
Design rules (max transition, capacitance, fan-out) first, then timing, then power and area. A smaller design that misses timing is useless, so timing comes before area.
12. How are multi-Vt cells used?
Low-Vt cells are fast but leak more; high-Vt cells are slow but leak less. Tools start with high or standard Vt and swap to low Vt only on critical paths, which keeps leakage under control.
13. How does automatic clock gating work?
When a group of flops is loaded only when an enable is true (a feedback mux), the tool replaces the mux with an integrated clock gating cell that stops the clock when the enable is false. It saves dynamic power on the clock and the flops. Tools usually only gate groups above a minimum width, because each gate has its own cost.
14. Flatten or keep the hierarchy?
Flattening lets the tool optimise across module boundaries, which often gives better timing and area. Keeping hierarchy makes debug, ECOs and equivalence checking easier, and is needed for blocks that are reused or implemented separately. Many teams keep the top levels and let the tool flatten small leaf modules.
15. What do dont_touch, dont_use and size_only do?
dont_touch stops the tool from modifying a cell or net (useful for hand-placed synchronisers or clock cells). dont_use removes library cells you don’t want, such as weak drivers or cells with bad layouts. size_only lets the tool resize a cell but not change its function or remove it.
16. How are clocks and resets treated in synthesis?
As ideal networks: the tool assumes zero delay and doesn’t buffer them, because clock tree synthesis and reset buffering are done properly in place and route. Clock uncertainty in SDC covers the expected skew until then.
Part 4: Checking the results
17. What do you check after a synthesis run?
- check_design: unconnected ports, multiple drivers, inferred latches, undriven nets.
- check_timing: unconstrained endpoints, missing clocks, combinational loops.
- Timing reports: worst negative slack and total negative slack, and which paths fail.
- Area and power reports, compared with the last good run.
18. What is logic equivalence checking (LEC)?
A formal check that the netlist implements exactly the same function as the RTL, without simulation. The tool maps matching points (flops, ports, black boxes) between the two designs and proves the logic between them is equivalent. Conformal and Formality are the common tools. It’s run after synthesis, after DFT insertion and after every ECO.
19. Synthesis shows negative slack. What do you do?
First check the constraints are right; a wrong clock or a missing false path is the most common cause. Then look at the failing paths: if the logic is simply too deep, fix the RTL (pipelining, restructuring, moving logic); if it’s close, the tool can usually close it with higher effort, multi-Vt cells or retiming.
20. Why does timing change between synthesis and place and route?
Real wire lengths, real clock trees with real skew, crosstalk, and buffering for placement all differ from synthesis estimates. Physical-aware synthesis narrows the gap, but you should still leave margin at synthesis.
21. How is DFT handled during synthesis?
Flops are replaced with scan flops, test control logic is added, and scan chains are defined. Chain ordering is often redone after placement to reduce wiring. Test-mode constraints are then added so STA can time both functional and scan modes.
22. How is FPGA synthesis different from ASIC synthesis?
FPGA synthesis maps onto fixed resources (LUTs, flip-flops, DSP blocks, block RAM) and the main goals are fitting and meeting timing. ASIC synthesis maps onto a standard cell library with much more freedom in sizing and cell choice, and power and area matter far more because they cost silicon.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
FAQ
Which synthesis tools should I know?
Synopsys Design Compiler and Fusion Compiler, and Cadence Genus, are the most common. Yosys is a free option that’s great for learning how RTL maps to gates.
Do RTL designers get synthesis questions?
Yes, mostly about coding style, latches, mismatches and how to fix timing in RTL. Synthesis engineers get the deeper flow and constraint questions.
How can I practise synthesis without a licence?
Run your RTL through Yosys and read the statistics and netlist. Seeing what your code becomes is the best way to learn.
What is the most common synthesis interview question?
Probably “what causes a simulation-synthesis mismatch?” followed by “how do you avoid a latch?”.
