The short answer: Ethernet interviews for VLSI roles focus on the MAC and PHY rather than networking theory: the frame format and size limits, why the minimum frame is 64 bytes, CRC-32, the inter-frame gap and line-rate calculations, MAC addresses and VLAN tags, the MII family of interfaces (GMII, RGMII, SGMII, XGMII), line coding, flow control with PAUSE frames, and how a MAC is built and verified.
Ethernet questions come up if you interview for networking chips, automotive SoCs, or any team that builds a MAC or PCS. You won’t be asked to configure routers; you’ll be asked how the bits on the wire are framed, checked and moved into the chip.
The frame format below is where nearly every Ethernet interview starts.
- Frames
- Rates and interfaces
- MAC design
- Verification
Table of Contents
Part 1: Frames
1. Which layers does Ethernet cover?
Layer 1 (the PHY) and layer 2 (the MAC). The PHY is split further into sublayers such as PCS (coding), PMA (serialisation) and PMD (the medium). The MAC and PHY talk through a media-independent interface, which is why there are so many “xMII” names.
2. What are the preamble and SFD for?
The 7-byte preamble of alternating 1s and 0s lets the receiver lock on to the bit timing; the 1-byte start frame delimiter marks where the frame begins. Neither is counted in the frame size.
3. Why is the minimum frame size 64 bytes?
For the original half-duplex CSMA/CD Ethernet, a sender had to still be transmitting when a collision from the far end of the cable came back, so frames had to last at least one slot time of 512 bit times, which is 64 bytes. Modern full-duplex links don’t have collisions, but the minimum stayed for compatibility. Shorter payloads are padded.
4. What is the maximum frame size?
1518 bytes for a standard frame (1500-byte payload), 1522 with one VLAN tag. Jumbo frames, commonly up to about 9000 bytes of payload, are widely supported but not part of the base standard.
5. What does the FCS check?
The frame check sequence is a CRC-32 computed over the destination address through the payload. The receiver recomputes it and drops frames that don’t match. In hardware, the CRC is calculated in parallel, several bytes per clock, using an unrolled form of the polynomial.
6. What is in a MAC address?
48 bits. The least significant bit of the first byte marks multicast (1) or unicast (0), and the next bit marks a locally administered address. All 1s is the broadcast address.
7. What is in an 802.1Q VLAN tag?
Four bytes inserted after the source address: a TPID of 0x8100, then 3 bits of priority (PCP), 1 bit DEI, and a 12-bit VLAN ID.
Part 2: Rates and interfaces
8. What is the maximum packet rate on a 1 Gb/s link?
Take the smallest frame and add the overhead on the wire:
64 (frame) + 8 (preamble + SFD) + 12 (IFG) = 84 bytes = 672 bits
1,000,000,000 / 672 = about 1.488 million packets per secondA MAC or switch that claims line rate must handle this back to back, which sets the clock frequency and datapath width.
9. What is the inter-frame gap?
At least 12 bytes (96 bit times) of idle between frames, giving the receiver time to finish processing. Some designs use a deficit idle count at higher speeds so the average gap stays at 12 bytes while frames align to the datapath.
10. What are MII, GMII, RGMII, SGMII and XGMII?
| Interface | Speed | Width and clock |
|---|---|---|
| MII | 10/100 Mb/s | 4 bits at 2.5 or 25 MHz |
| GMII | 1 Gb/s | 8 bits at 125 MHz |
| RGMII | 1 Gb/s | 4 bits on both edges of 125 MHz |
| SGMII | 1 Gb/s | One serial pair at 1.25 Gbaud, 8b/10b |
| XGMII | 10 Gb/s | 32 bits at 156.25 MHz, double data rate |
Higher speeds use serial interfaces such as XAUI, USXGMII and multi-lane SerDes.
11. Which line codes are used?
1 Gb/s fibre (1000BASE-X) and SGMII use 8b/10b. 10G and faster BASE-R links use 64b/66b, which has much less overhead. The fastest links add forward error correction, and PAM4 signalling at 50 Gb/s per lane and above.
12. What does auto-negotiation do?
On twisted-pair links, the two ends exchange their capabilities (speed, duplex, pause support) and pick the best common mode before the link comes up.
Part 3: MAC design
13. What does an Ethernet MAC contain?
- Transmit path: frame assembly, padding, CRC generation, IFG insertion.
- Receive path: preamble stripping, CRC checking, length checks, address filtering.
- FIFOs between the system clock and the line clock.
- Flow control (PAUSE) handling and statistics counters.
- Often IEEE 1588 timestamping for time synchronisation.
14. Why does a MAC need FIFOs?
The line side runs at a fixed rate and can’t be stalled in the middle of a frame, while the system bus has its own clock and may have backpressure. FIFOs absorb the difference and also cross the clock domains (usually as asynchronous FIFOs).
15. What is flow control in Ethernet?
IEEE 802.3x PAUSE frames tell the link partner to stop sending for a given time. Priority flow control (802.1Qbb) pauses individual traffic classes instead of the whole link, which data-centre networks rely on.
16. Store-and-forward or cut-through?
A store-and-forward switch receives the whole frame and checks the CRC before forwarding it, so bad frames are dropped, at the cost of latency. A cut-through switch starts forwarding as soon as it has read the destination address, cutting latency but passing on frames that turn out to be corrupt.
17. What is IEEE 1588 (PTP)?
The Precision Time Protocol synchronises clocks across a network. Hardware timestamps frames as close to the wire as possible, in the MAC or PHY, so the timing isn’t blurred by software delays. Time-Sensitive Networking (TSN) builds on it for automotive and industrial networks.
Part 4: Verification
18. How would you verify an Ethernet MAC?
- Use an Ethernet VIP or a reference model on the line side, and a bus VIP on the system side.
- Check frames end to end with a scoreboard, including padding and CRC.
- Send back-to-back frames with the minimum IFG at full line rate.
- Inject errors: bad CRC, runt and oversized frames, missing SFD, link drops in the middle of a frame.
- Cover PAUSE frames, VLAN tags, address filtering modes and every speed the MAC supports.
Practise this on VLSI Forge
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FAQ
Which VLSI roles get Ethernet questions?
Design and verification engineers in networking, data-centre, automotive and industrial chip teams, especially those working on MAC, PCS or switch logic.
Do I need to know TCP/IP for these interviews?
Rarely. The focus is layers 1 and 2. Knowing what an IP header is helps if the chip parses packets, but MAC and PHY questions dominate.
What calculation should I practise?
The line-rate calculation with preamble, SFD and IFG, at different speeds and frame sizes.
What is the most common Ethernet interview question?
Why the minimum frame is 64 bytes, followed by the frame format and CRC.
