The short answer: STA models a clock with its period and waveform plus the delays and uncertainties around it. Latency (insertion delay) is the time from the clock source to a register’s clock pin: source latency before the clock definition point, network latency through the clock tree. Skew is the difference in latency between two related registers. Jitter is cycle-to-cycle variation of the clock edge from the PLL and supply noise. Before CTS, clocks are ideal and set_clock_uncertainty covers expected skew and jitter; after CTS, real latency is propagated and uncertainty covers jitter and margin.
Clocks are where most timing confusion starts, because the same idea has several names (latency and insertion delay, uncertainty and margin). This post puts them together. It replaces six older posts: clock networks, skew, latency, uncertainty, insertion delay and jitter.
For how clock trees are built, see clock tree synthesis in my PD series.
- Latency and skew
- Defining clocks
- Skew: good, bad and useful
- Jitter and uncertainty
- Clock transition and other clock checks
Table of Contents
Part 1: Latency and skew
Part 2: Defining clocks
create_clock -name clk -period 2.0 -waveform {0 1.0} [get_ports clk]
create_generated_clock -name clk_div2 -source [get_ports clk] \
-divide_by 2 [get_pins u_div/q_reg/Q]
set_clock_latency -source 0.30 [get_clocks clk] ;# outside the block
set_clock_latency 0.50 [get_clocks clk] ;# network latency, pre-CTS estimate
set_clock_uncertainty -setup 0.10 [get_clocks clk]
set_clock_uncertainty -hold 0.05 [get_clocks clk]
set_clock_transition 0.08 [get_clocks clk] ;# ideal-clock slew, pre-CTSAfter CTS, replace the network latency estimate with set_propagated_clock [all_clocks] so STA uses the real tree delays.
Part 3: Skew: good, bad and useful
- Positive skew (capture clock later than launch) gives setup more time and takes it away from hold.
- Negative skew does the opposite.
- Only skew between flops that talk to each other matters (local skew); global skew across unrelated flops is irrelevant for timing.
- Useful skew: deliberately shifting clock arrival to borrow time for a critical stage from a neighbour with spare slack.
Part 4: Jitter and uncertainty
| Term | What it is | How STA handles it |
|---|---|---|
| Period jitter | Variation of one period from nominal | Part of setup uncertainty |
| Cycle-to-cycle jitter | Difference between consecutive periods | Part of setup uncertainty |
| Pre-CTS skew | Unknown until the tree exists | Added to uncertainty before CTS, removed after |
| Margin | Extra safety the team chooses | Added to uncertainty |
Hold uncertainty usually doesn’t include period jitter, because launch and capture happen on the same edge; it covers skew estimates and margin.
Part 5: Clock transition and other clock checks
Slow clock edges add delay, increase variation and burn short-circuit power, so max transition limits on clock nets are tight. STA also checks minimum pulse width (high and low phases long enough for each flop), minimum period, and clock gating checks on clock-enable logic, covered in clock gating checks.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Previous in my STA series: Cell and wire delay calculation. Next: SDC timing constraints.
FAQ
What is clock latency?
The delay from the clock source to a register’s clock pin: source latency plus network (clock tree) latency. It’s also called insertion delay.
What is clock skew?
The difference in clock arrival time between two registers, usually a launch and a capture register on the same path.
What is the difference between skew and jitter?
Skew is a spatial difference between two clock pins in the same cycle; jitter is variation of the clock edge itself over time.
What does set_clock_uncertainty model?
Jitter, and before CTS the expected skew, plus any extra margin the team wants on setup or hold.
