The short answer: STA calculates each stage’s delay as the driving cell’s delay plus the delay of the wire it drives. Cell delay and output slew come from the Liberty library, looked up by input slew and output load in non-linear delay model (NLDM) tables, or computed from current-source models (CCS or ECSM) for better accuracy. Wire delay comes from the extracted RC network using models like Elmore delay or higher-order reduction. Slew is propagated from stage to stage, and at advanced nodes each delay also carries a variation (sigma) from LVF data.
Every number in a timing report comes from a delay calculation. You rarely do it by hand, but knowing how it works explains why a cell is slow, why a long wire hurts more than its length suggests, and why slew matters so much. This post replaces my older delay calculation post.
- The ingredients
- Cell delay: NLDM tables
- Wire delay and effective capacitance
- Slew propagation
- Rise, fall and unateness
- Why it matters in practice
Table of Contents
Part 1: The ingredients
Part 2: Cell delay: NLDM tables
cell (NAND2X1) {
pin (Y) {
timing () {
related_pin : "A";
cell_rise (delay_template_3x3) {
index_1 ("0.01, 0.05, 0.20"); /* input slew, ns */
index_2 ("0.002, 0.010, 0.040"); /* output load, pF */
values ("0.020, 0.035, 0.080", \
"0.028, 0.044, 0.091", \
"0.055, 0.072, 0.120");
}
...
}
}
}The tool interpolates between table points (and extrapolates outside them, which is less accurate; that’s one reason for max transition limits). Separate tables give rise and fall delays and output transitions, for each input pin.
Part 3: Wire delay and effective capacitance
- A wire is a distributed RC network. The Elmore delay to a sink is the sum, over each resistor on the path, of the resistance times all the capacitance downstream of it.
- Because of wire resistance, the driver doesn’t see the full wire capacitance at once; tools compute an effective capacitance for the table lookup.
- For long or resistive nets, current-source models (CCS, ECSM) model the driver’s output waveform more accurately than NLDM.
Part 4: Slew propagation
The output slew of one stage is the input slew of the next, and a slower input slew increases the next cell’s delay. STA propagates slews along the path; graph-based analysis uses the worst slew arriving at each pin, which is pessimistic, and path-based analysis recomputes slews along the actual path to remove that pessimism.
Part 5: Rise, fall and unateness
A positive-unate arc (like a buffer) passes a rising input to a rising output; a negative-unate arc (like an inverter or NAND) inverts it; a non-unate arc (like an XOR) can do either. STA follows these rules so that rise and fall delays combine correctly along a path.
Part 6: Why it matters in practice
- Weak drivers on big loads give large slews that slow several stages, not just one.
- Long thin wires add delay quadratically with length, which is why buffering long nets helps.
- Library accuracy matters: wrong or extrapolated tables give wrong timing, so keep slews and loads inside characterised ranges.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Static Timing Analysis problems · Daily challenge
Previous in my STA series: Arrival time, required time and slack. Next: Clocks in STA: latency, skew, jitter.
FAQ
How does STA calculate cell delay?
By looking up delay and output slew in the cell’s Liberty tables using the input slew and output load, or by using current-source models for higher accuracy.
What is NLDM?
The non-linear delay model: Liberty tables of delay and transition indexed by input slew and output capacitance.
What is Elmore delay?
A first-order estimate of RC wire delay: for each resistor, its resistance times the total capacitance downstream, summed along the path.
Why does slew matter?
A slow input transition increases the delay of the receiving cell and its output slew, so a bad slew slows every following stage.
