What Is Verilog? A Practical Introduction for Beginners

The short answer: Verilog is a hardware description language (HDL): you use it to describe digital circuits, not to write a program that runs step by step. The same Verilog code is simulated to check that the design works, then synthesised into real logic gates for an ASIC or an FPGA. It’s standardised as IEEE 1364 and is now part of SystemVerilog (IEEE 1800), and it’s the most widely used HDL in the chip industry.

When I started with Verilog, the hardest part wasn’t the syntax. It was the mindset. Verilog looks like C, but almost nothing in it runs “line by line”. Every always block and every assign is a piece of hardware, and they all work at the same time.

This post is the first in my Verilog series. I’ll explain what Verilog is, how code becomes a chip, and how I’d learn it today.

1. What a hardware description language does
2. How Verilog code becomes a chip
3. A short history
4. Verilog, VHDL or SystemVerilog?
5. Tools to start with
6. How I’d learn Verilog: this series in order

Part 1: What a hardware description language does

In software, you write instructions for a processor that already exists. In Verilog, you describe the processor (or any other circuit) itself: which wires connect where, which logic sits between them, and which flip-flops store state on each clock edge.

module and_gate (
  input  wire a,
  input  wire b,
  output wire y
);
  assign y = a & b;   // this is a real AND gate, always active
endmodule

That assign isn’t executed once; it describes a gate whose output follows its inputs all the time. Keeping that picture in mind avoids most beginner mistakes.

Part 2: How Verilog code becomes a chip

• Simulation runs your design with a testbench and shows waveforms, so you can check it does what the spec says.
• Synthesis turns the RTL into a netlist of gates and flip-flops from a cell library (ASIC) or into LUTs and flops (FPGA).
• Implementation places and routes that netlist. For an ASIC it ends in a layout sent for fabrication; for an FPGA, in a bitstream.

Only a subset of Verilog can be synthesised. Things like delays (#10) and $display are for simulation and testbenches only. I’ll point these out as we go.

Part 3: A short history

• Verilog was created at Gateway Design Automation in the mid-1980s as a simulation language.
• Cadence acquired Gateway and later opened the language, and it became an IEEE standard: IEEE 1364-1995, revised in 2001 and 2005.
• In 2009 Verilog was merged into SystemVerilog (IEEE 1800), which adds features for design and, especially, verification. Today “Verilog” in job descriptions usually means the synthesisable core that both share.

Part 4: Verilog, VHDL or SystemVerilog?

If you’re aiming for ASIC design or verification jobs, I’d learn Verilog first, then move to SystemVerilog. The concepts carry over directly.

Part 5: Tools to start with

• Icarus Verilog and Verilator: free simulators.
• GTKWave or Surfer: free waveform viewers.
• Yosys: free synthesis, great for seeing what your code turns into.
• VLSI Forge: I built it so you can write Verilog in the browser, run it on a real simulator and see waveforms without installing anything.

Part 6: How I’d learn Verilog: this series in order

Each post builds on the previous one, and each has small, synthesisable examples.

1. What is Verilog?
2. Verilog syntax, comments and numbers
3. Verilog data types
4. Verilog operators
5. Modules, ports and hierarchy
6. Levels of modelling in Verilog
7. Dataflow modelling and continuous assignments
8. initial and always blocks
9. Blocking vs non-blocking assignments
10. if, case and loops
11. Writing combinational logic
12. Flip-flops, latches, registers and counters
13. FSMs in Verilog
14. Delays and timing checks
15. Tasks and functions
16. parameter, localparam and define
17. System tasks
18. Coding guidelines for synthesisable RTL

Next: Verilog syntax, comments and numbers.

FAQ

Is Verilog a programming language?

Not in the usual sense. It’s a hardware description language: it describes circuits that work in parallel, though its syntax looks like C.

How long does it take to learn Verilog?

The basics take a few weeks of regular practice. Writing clean, synthesisable RTL with confidence takes a few months of real designs.

Is Verilog still used?

Yes. It’s the base of SystemVerilog and the most common language for RTL design in the chip industry.

Do I need to know digital electronics first?

Yes, at least gates, flip-flops, counters and FSMs. Verilog describes hardware, so you need to know what hardware you want.