How and when to use parameter, localparam and `define in Verilog, with examples, macro pitfalls, include guards, conditional compilation and other compiler directives.
Browsing: Hardware Description Language
How delays work in Verilog: timescale, inter vs intra-assignment delays, inertial vs transport delays with waveforms, rise and fall delays, specify blocks and $setup, $hold and $width.
Verilog templates for flip-flops (async and sync reset, enable), latches, registers, shift registers, pipelines and counters, with rules for sequential blocks.
How to write combinational logic in Verilog: a five-step checklist, ALU, priority encoder, decoder and mux examples, avoiding latches and loops, and thinking about timing.
Continuous assignments in Verilog explained: what assign means in hardware, the rules, practical examples (adders, muxes, decoders), assign vs always @(*) and common mistakes.
Verilog’s basic syntax rules in one place: comments, identifiers, keywords, sized and unsized numbers, x and z values, strings and the mistakes beginners make most.
What Verilog is, how Verilog code becomes a chip, a short history, Verilog vs VHDL vs SystemVerilog, free tools to start with, and a learning path.