Wire parasitics and crosstalk explained: resistance and capacitance, extraction and SPEF, coupling capacitance, delta delay, noise glitches, timing windows and how to fix crosstalk.
Author: Raju Gorla
Routing explained: global routing, track assignment, detailed routing, routing algorithms, metal layers, vias and redundant vias, special nets and post-route steps.
Clock tree synthesis explained: CTS goals and constraints, skew, latency and jitter, useful skew, tree, H-tree and mesh structures, clock gating and post-CTS steps.
Placement explained: global placement, legalisation and detailed placement, what the placer optimises, congestion causes and fixes, and pre-CTS checks.
Power planning explained: the structure of a power grid, sizing straps for IR drop and EM, macros and multiple domains, decoupling capacitors and power network checks.
Floorplanning explained: die and core sizing, chip partitioning, macro placement guidelines, I/O and pin placement, blockages and halos, and how to check a floorplan.
Everything a physical design run needs: netlist, SDC, Liberty, LEF, RC models, UPF, what’s inside a PDK, the commercial and open-source PD tools, and pre-flow sanity checks.
What physical design is, where it sits in the chip flow, the main steps from floorplan to sign-off, PPA trade-offs, tools and what PD engineers do.