The short answer: Power planning builds the network that delivers VDD and ground to every cell: rings around the core and macros, wide straps on the upper metal layers, thin rails on M1 along every standard-cell row, and stacks of vias connecting them. It’s sized so that IR drop stays within budget (often a few percent of the supply) and current density stays within electromigration limits. Decoupling capacitor cells are added to supply sudden current demands locally.
A design that meets timing but can’t get enough current to its cells will fail in silicon. The power grid is planned early, during floorplanning, because it uses a lot of routing resources and is hard to change later. This post combines my older posts on power planning, power grid design and decoupling capacitors.
- The structure of a grid
- Sizing the grid
- Macros and multiple domains
- Decoupling capacitors
- Checks for the power network
Table of Contents
Part 1: The structure of a grid
Part 2: Sizing the grid
- Estimate the block’s current from its power: I = P / V. A 1 W block at 0.8 V draws about 1.25 A.
- Pick strap width and pitch so the resistance from the supply pins to any cell keeps static IR drop inside budget.
- Use the thick top metals for the main distribution; they have the lowest resistance.
- Leave enough routing tracks between straps for signals; the grid can easily take a large share of the upper layers.
- Check current density against the electromigration rules for each layer and via.
Part 3: Macros and multiple domains
Macros usually get their own rings and connect to the main grid through their power pins. Designs with several voltage domains or power-gated regions need separate grids, power switch cells placed in a pattern across the switchable domain, and always-on supplies for retention and isolation cells. These all come from the UPF power intent.
Part 4: Decoupling capacitors
When many cells switch at once, the grid can’t deliver the current instantly through its resistance and inductance, so the local supply dips (dynamic IR drop). Decap cells are small on-chip capacitors between VDD and VSS placed near busy logic: they supply that current locally. They cost area and leak, so they’re added where dynamic IR analysis shows they’re needed, often in filler space after placement.
Part 5: Checks for the power network
| Check | What it catches |
|---|---|
| Connectivity (PG verification) | Floating straps, missing vias, unconnected macro pins |
| Static IR drop | Average voltage loss from resistance |
| Dynamic IR drop | Local dips when many cells switch together |
| Electromigration | Current density over the limit on wires and vias |
IR drop and EM get their own post later in the series: IR drop and electromigration.
Practise this on VLSI Forge
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Physical Design problems · Static Timing Analysis problems
Previous in my physical design series: Floorplanning. Next: Placement.
FAQ
What is power planning in physical design?
Designing the network of rings, straps, rails and vias that delivers supply and ground to every cell with acceptable IR drop and current density.
What are power straps and rails?
Straps are wide wires on upper metal layers that distribute current across the block; rails are thin M1 wires along each cell row that feed the cells.
Why are decoupling capacitors needed?
To supply sudden current demands locally and reduce dynamic IR drop when many cells switch at once.
When is power planning done?
During floorplanning, before placement, because the grid uses significant routing resources and is hard to change later.
