The short answer: Physical design (PD) turns a synthesised gate-level netlist into a manufacturable layout. It starts with floorplanning (die size, macros, I/O and the power grid), then places standard cells, builds the clock trees (CTS), routes every connection in metal, and finally signs off timing, power integrity and physical rules (DRC, LVS) before the layout is released as GDSII or OASIS for mask making. The goal throughout is to meet performance, power and area (PPA) targets.
In the front end, engineers decide what the chip does. In physical design, we decide where every one of its millions or billions of transistors goes and how they’re wired. It’s the part of the flow where physics (wire delays, voltage drop, manufacturing rules) catches up with the logic.
This is the first post in my physical design series. It replaces my older posts on what PD is, PD in the VLSI flow, and front end vs back end.
- Where PD sits in the chip flow
- The flow
- PPA: the goals behind every decision
- Tools
- What a PD engineer does day to day
- This series in order
Table of Contents
Part 1: Where PD sits in the chip flow
Front end: specification, RTL design, verification and synthesis. Back end: physical design, sign-off and tape-out. Synthesis is the hand-off point: it produces the netlist and timing constraints that PD starts from. DFT insertion usually happens during synthesis, and scan chains are reordered during placement.
| Front end | Back end (PD) | |
|---|---|---|
| Works on | RTL, testbenches | Netlist, layout database |
| Main questions | Is the function right? | Does it fit, meet timing and power, and can it be manufactured? |
| Main tools | Simulators, synthesis | Place and route, STA, IR/EM, physical verification |
| Output | Netlist + constraints | GDSII/OASIS layout |
Part 2: The flow
- Floorplanning: die and core size, macro placement, I/O, and the power network.
- Placement: standard cells go into rows while the tool optimises timing, congestion and power.
- Clock tree synthesis: buffers and inverters build clock networks with controlled skew and latency.
- Routing: every net is connected on the metal layers, respecting design rules.
- Sign-off: static timing analysis with extracted parasitics, IR drop and electromigration, DRC, LVS and other checks, then tape-out.
Part 3: PPA: the goals behind every decision
Every step trades performance (timing), power and area. A bigger floorplan eases congestion but costs area; more buffering fixes timing but costs power; low-Vt cells are faster but leak more. Much of a PD engineer’s skill is knowing which trade-off to make, and when.
Part 4: Tools
The main commercial place-and-route platforms are Cadence Innovus and Synopsys Fusion Compiler (and IC Compiler II). Sign-off uses tools such as PrimeTime or Tempus for timing, RedHawk or Voltus for power integrity, and Calibre, ICV or Pegasus for physical verification. OpenROAD is a capable open-source flow and is great for learning.
Part 5: What a PD engineer does day to day
- Runs and tunes the flow for a block, step by step.
- Analyses timing, congestion and power reports, and fixes problems.
- Works with RTL designers on floorplan-friendly partitioning and timing-critical paths.
- Writes Tcl scripts to automate and debug the flow.
- Closes the block to sign-off and hands it to the top-level team.
More in my post on the physical design engineer role.
Part 6: This series in order
- What is physical design?
- PD inputs: PDK, libraries and tools
- Floorplanning
- Power planning
- Placement
- Clock tree synthesis
- Routing
- Parasitics and crosstalk
- Timing closure and ECOs
- Sign-off timing and MCMM
- IR drop and electromigration
- Physical verification
- PPA and low-power PD
- Tape-out and mask preparation
- Advanced nodes and 3D ICs
- Tcl scripting for PD
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Next: PD inputs: PDK, libraries and tools.
FAQ
What is physical design in VLSI?
The process of converting a gate-level netlist into a physical layout that meets timing, power, area and manufacturing rules.
What are the main steps of physical design?
Floorplanning, placement, clock tree synthesis, routing and sign-off.
What is the input and output of physical design?
Inputs: netlist, timing constraints (SDC), technology files and libraries. Output: a GDSII or OASIS layout, plus netlists and reports for sign-off.
Is physical design a good career?
Yes. Every chip needs it, it’s a large job market, and PD skills (timing, power, scripting) are valued across the industry.
