The short answer: Placement puts every standard cell into a legal position in the cell rows. Global placement finds rough positions that keep connected cells close while spreading density; legalisation snaps cells onto rows and sites without overlap; detailed placement refines locally. Throughout, the tool optimises timing (sizing, buffering, Vt swaps), fixes design-rule violations like max transition, and manages congestion so the design can be routed. Scan chains are reordered and the clock network is estimated before CTS.
Placement decides most of a block’s wire lengths, and wire length decides timing, power and routability. This post combines my older posts on standard cell placement, legalisation, congestion analysis and clock-tree-aware placement.
- The steps
- What the placer optimises
- Legalisation
- Congestion
- Before CTS
- What I look at after placement
Table of Contents
Part 1: The steps
Part 2: What the placer optimises
- Wirelength: connected cells close together; shorter wires mean less delay and power.
- Timing: critical paths get priority; cells on them are pulled together and upsized.
- Density: cells are spread so local utilisation doesn’t make routing impossible.
- Congestion: the tool estimates routing demand and spreads cells where demand exceeds supply.
- Power: high-activity nets are kept short; low-Vt cells are used only where timing needs them.
Part 3: Legalisation
Global placement allows overlaps and off-grid positions. Legalisation moves every cell to a valid site in a row with the right orientation and power-rail alignment, honouring blockages, fixed cells, endcaps and well taps, and multi-height cell rules. Moving cells changes timing, so the tool re-optimises afterwards.
Part 4: Congestion
Congestion means more wires want to pass through an area than it has routing tracks. It shows up as overflow in the global route map. Common causes and fixes:
| Cause | Fix |
|---|---|
| High local cell density | Lower utilisation, partial blockages, cell padding |
| Pin-dense cells (complex gates, flops) | Spread them, use cell padding or density screens |
| Narrow channels between macros | Widen channels or block them fully |
| Many long nets through one area | Change the floorplan or pin locations |
| Logic with high fan-in/fan-out (e.g. muxes) | Restructure in synthesis or RTL |
Part 5: Before CTS
- Timing checked with ideal clocks and uncertainty for the expected skew; aim for small negative or positive slack, because CTS and routing usually make timing worse.
- Clock-tree-aware placement keeps flops of the same clock close together and leaves room for clock buffers.
- Scan chains reordered by location to cut wiring.
- Max transition, capacitance and fan-out fixed.
- Tie cells inserted for constant inputs.
Part 6: What I look at after placement
The congestion map, the worst timing paths and whether their cells are spread across the block, cell density hotspots, and utilisation per region. If the same paths fail in every run, the fix is usually in the floorplan or RTL, not in placement settings.
Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
Physical Design problems · Static Timing Analysis problems
Previous in my physical design series: Power planning. Next: Clock tree synthesis.
FAQ
What is placement in physical design?
The step that assigns every standard cell a legal location in the cell rows while optimising wirelength, timing, congestion and power.
What is legalisation?
Moving placed cells to valid sites on rows with no overlaps, respecting blockages and technology rules.
What causes routing congestion?
High cell density, pin-dense cells, narrow channels between macros and many long nets passing through the same area.
Why is timing checked with ideal clocks before CTS?
Because the real clock tree doesn’t exist yet; the tool uses clock uncertainty to account for the skew CTS will add.
