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Physical Design

Tcl Scripting for Physical Design: Queries, Floorplans and Flows

Raju GorlaBy Raju Gorla18 June 2026Updated:11 October 2026No Comments4 Mins Read
Tcl scripting for physical design
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The short answer: Tcl is the command language of every major physical design tool, so PD engineers use it to run the flow stage by stage, build floorplans from parameters, query the design database (cells, nets, pins and their attributes), produce custom reports across runs, make scripted ECOs and run sanity checks before hand-off. The core language is the same everywhere; object queries differ between tools (for example get_cells and collections in Synopsys tools, get_db in Cadence Innovus).

You can run a P&R tool from its GUI, but you can’t close a real block that way. Every serious PD flow is a set of Tcl scripts, and the engineers who write good ones close faster. This is the last post in my physical design series. For core Tcl (lists, procs, regexp), see my Tcl interview questions.

  1. What gets scripted
  2. Querying the design
  3. Scripting a floorplan
  4. Structuring a flow
  5. Good scripting habits

Table of Contents

  • Part 1: What gets scripted
  • Part 2: Querying the design
  • Part 3: Scripting a floorplan
  • Part 4: Structuring a flow
  • Part 5: Good scripting habits
  • FAQ
    • Why is Tcl used in physical design?
    • Is Tcl the same in Innovus and Fusion Compiler?
    • What should I learn first for PD scripting?
    • Should PD engineers learn Python?

Part 1: What gets scripted

What physical design engineers script in Tcl: flow scripts, floorplan setup, queries, reports, ECOs and checks
Six kinds of PD scripts.

Part 2: Querying the design

Examples in Synopsys-style syntax; Cadence Innovus has equivalents with get_db.

# nets with high fan-out
foreach_in_collection n [get_nets -hierarchical -filter "number_of_leaf_loads > 64"] {
    puts "[get_object_name $n] [get_attribute $n number_of_leaf_loads]"
}

# count cells by threshold-voltage flavour (library naming varies)
foreach vt {LVT SVT HVT} {
    set n [sizeof_collection [get_cells -hierarchical -filter "ref_name =~ *$vt*"]]
    puts "$vt cells: $n"
}

# worst 10 setup paths, one line each
foreach_in_collection p [get_timing_paths -max_paths 10 -delay_type max] {
    puts [format "%-50s %8.3f" [get_object_name [get_attribute $p endpoint]] [get_attribute $p slack]]
}

Attribute names differ between tools and versions; list them with the tool’s attribute-listing command before scripting.

Part 3: Scripting a floorplan

# place a row of macros along the top edge, from parameters
set x0 50.0 ; set y_top 1950.0 ; set gap 20.0
foreach m {u_sram0 u_sram1 u_sram2 u_sram3} {
    set w [get_attribute [get_cells $m] width]
    set h [get_attribute [get_cells $m] height]
    set_attribute [get_cells $m] origin [list $x0 [expr {$y_top - $h}]]
    set_attribute [get_cells $m] orientation MX
    set_attribute [get_cells $m] is_fixed true
    set x0 [expr {$x0 + $w + $gap}]
}

Commands for placing macros vary by tool, but the idea is the same: compute positions from parameters, so a floorplan change is a one-line edit, not an afternoon of dragging.

Part 4: Structuring a flow

  • One script per stage (init, floorplan, place, cts, route, signoff), each saving a database at the end.
  • A shared settings file for libraries, corners, modes and tool options.
  • Reports written to predictable paths, so a summary script can compare runs.
  • Every stage checks its inputs and fails loudly, instead of continuing with a broken design.

Part 5: Good scripting habits

  • Filter inside the tool (-filter) instead of looping over everything in Tcl; it’s much faster on large designs.
  • Use procs with clear arguments and put them in a namespace.
  • Print what the script did (“resized 42 cells”), so silent no-ops are obvious.
  • Keep scripts in version control alongside the design.
  • Learn Python too for regression management and data analysis around the tools.

Practise this on VLSI Forge

I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.

Physical Design problems · Static Timing Analysis problems

Previous in my physical design series: Advanced nodes and 3D ICs. That’s the end of my physical design series.

FAQ

Why is Tcl used in physical design?

Because P&R, STA and verification tools use Tcl as their command language, so flows, queries, reports and ECOs are all scripted in it.

Is Tcl the same in Innovus and Fusion Compiler?

The core language is the same, but object query commands and attribute names differ between tools.

What should I learn first for PD scripting?

Core Tcl (lists, loops, procs, regexp, file handling), then your tool’s collection and attribute commands.

Should PD engineers learn Python?

Yes. Tcl runs inside the tools; Python is widely used for regression management, report parsing and data analysis around them.

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Previous ArticleAdvanced Nodes and 3D ICs: FinFET, GAA, Backside Power and Chiplets
Next Article What Is UVM? A Practical Introduction to the Universal Verification Methodology
Raju Gorla
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