Placement explained: global placement, legalisation and detailed placement, what the placer optimises, congestion causes and fixes, and pre-CTS checks.
Browsing: Job Roles
Power planning explained: the structure of a power grid, sizing straps for IR drop and EM, macros and multiple domains, decoupling capacitors and power network checks.
Floorplanning explained: die and core sizing, chip partitioning, macro placement guidelines, I/O and pin placement, blockages and halos, and how to check a floorplan.
Everything a physical design run needs: netlist, SDC, Liberty, LEF, RC models, UPF, what’s inside a PDK, the commercial and open-source PD tools, and pre-flow sanity checks.
What physical design is, where it sits in the chip flow, the main steps from floorplan to sign-off, PPA trade-offs, tools and what PD engineers do.
How latches change timing: transparent capture, time borrowing and how STA computes it, a worked example, set_max_time_borrow, and where latches appear in real designs.
Clock gating checks explained with a waveform: setup and hold on AND and OR gates, integrated clock gating cells, why enable paths are often critical, and other clock checks.
How to read a timing report, a step-by-step order for debugging setup and hold violations, useful report options, typical causes and fixes, and other violations to check.
How STA covers variation: PVT and RC corners, worst-case vs best-case analysis, temperature inversion, OCV derates, AOCV, POCV and LVF, and CRPR.
Timing exceptions explained: when to use false paths, how multicycle paths work (and why they need a hold adjustment), max delay and clock groups, and rules for writing safe exceptions.