How Verilog procedural blocks work: initial vs always, event control with @, # and wait, begin-end vs fork-join, and the rules I follow for always blocks in RTL.
Browsing: Verilog
Continuous assignments in Verilog explained: what assign means in hardware, the rules, practical examples (adders, muxes, decoders), assign vs always @(*) and common mistakes.
The same 2:1 mux written at switch, gate, dataflow and behavioural level, plus user-defined primitives, structural modelling and which level to use when.
How to define Verilog modules, declare ports, instantiate modules with named connections and parameters, build a hierarchy, and use generate for repeated instances.
Every Verilog operator with examples: bitwise vs logical vs reduction, shifts, concatenation, precedence, expression width, signed arithmetic and what each operator synthesises to.
Verilog data types explained: the four values, nets vs variables, wire vs reg, vectors and part selects, signed types, integer and real, arrays and memories, and implicit nets.
Verilog’s basic syntax rules in one place: comments, identifiers, keywords, sized and unsized numbers, x and z values, strings and the mistakes beginners make most.
What Verilog is, how Verilog code becomes a chip, a short history, Verilog vs VHDL vs SystemVerilog, free tools to start with, and a learning path.