Browsing: Digital Design

Verilog tasks vs functions explained with examples: return values, timing controls, synthesis, how arguments are passed, and static vs automatic.

How delays work in Verilog: timescale, inter vs intra-assignment delays, inertial vs transport delays with waveforms, rise and fall delays, specify blocks and $setup, $hold and $width.

How to code FSMs in Verilog: the three parts of a state machine, a complete traffic light controller, one vs two vs three-block styles, state encoding and common mistakes.

Verilog templates for flip-flops (async and sync reset, enable), latches, registers, shift registers, pipelines and counters, with rules for sequential blocks.

How to write combinational logic in Verilog: a five-step checklist, ALU, priority encoder, decoder and mux examples, avoiding latches and loops, and thinking about timing.

Verilog if-else, case, casez and loops explained with the hardware they create: priority logic, muxes, unrolled loops, and how to avoid latches.

Blocking (=) vs non-blocking (<=) assignments explained with waveforms, the Verilog scheduling regions behind them, race conditions, and the rules to follow in RTL.

How Verilog procedural blocks work: initial vs always, event control with @, # and wait, begin-end vs fork-join, and the rules I follow for always blocks in RTL.

Continuous assignments in Verilog explained: what assign means in hardware, the rules, practical examples (adders, muxes, decoders), assign vs always @(*) and common mistakes.

The same 2:1 mux written at switch, gate, dataflow and behavioural level, plus user-defined primitives, structural modelling and which level to use when.