Browsing: Digital Design

Comparators, array, Booth and Wallace-tree multipliers, and how an ALU works, with Verilog.

Half and full adders, ripple-carry vs carry-lookahead, subtraction with two’s complement, and adders in Verilog.

What combinational logic is, the five-step design process, a worked majority-voter example in Verilog, and common pitfalls.

How CMOS gates are built from PMOS and NMOS transistors, NAND vs NOR, where power goes, and how logic families compare.

Truth tables for every logic gate, what each is used for, why NAND and NOR are universal, and gates in Verilog.

How K-maps work, a worked 4-variable example, the grouping rules, don’t-cares, and what tools use beyond K-maps.

The Boolean algebra laws you will actually use, a worked simplification, De Morgan’s theorems and SOP vs POS.

The Verilog coding guidelines I follow for synthesisable RTL: clocks, resets, combinational and sequential logic, synthesis rules, readability and lint.

The Verilog system tasks I actually use: $display vs $strobe vs $monitor, format specifiers, $finish, file I/O, $readmemh, waveform dumping, $random and $clog2.

How and when to use parameter, localparam and `define in Verilog, with examples, macro pitfalls, include guards, conditional compilation and other compiler directives.