RTL Design Interview Questions (with Answers)

The short answer: RTL design interviews mostly test six areas: finite state machines, FIFOs, clock domain crossing, Verilog coding style (blocking vs non-blocking, latches), timing (setup, hold, pipelining) and resets. Below are the questions I would expect, with short answers you can build on. For each one, be ready to draw a diagram or write the code.

I have grouped these by topic rather than listing a hundred random questions. Learn the reasoning behind each answer, because good interviewers will always ask a follow-up.

1. The topics that come up most
2. Verilog coding style
3. FSMs
4. FIFOs and CDC
5. Timing
6. Resets and low power
7. How to prepare

Part 1: The topics that come up most

Part 2: Verilog coding style

What is the difference between blocking and non-blocking assignments?

Blocking (=) updates immediately, in order. Non-blocking (<=) schedules all updates for the end of the time step. Use non-blocking for sequential logic and blocking for combinational logic, so simulation matches the hardware and you avoid race conditions.

How do you accidentally create a latch?

By not assigning a variable in every path of a combinational always block, for example a missing else or a case statement without a default. The tool then has to remember the old value, which means a latch.

Why should a combinational always block use always @(*)?

So the sensitivity list includes every input automatically. A missing signal in a manual list causes simulation to differ from synthesis.

What does synthesisable mean?

Code that a synthesis tool can turn into gates and flops: no delays (#10), no initial blocks for logic in ASICs, no file operations, and loops with fixed bounds.

Part 3: FSMs

What is the difference between Mealy and Moore machines?

A Moore machine’s outputs depend only on the current state; a Mealy machine’s outputs depend on the state and the inputs. Mealy can react a cycle earlier with fewer states, but its outputs can glitch with the inputs, so they are often registered.

Which state encoding would you use?

Binary uses the fewest flops; one-hot uses one flop per state but has simpler, faster next-state logic and is common in FPGAs; Gray suits sequential state changes. Say which you would choose and why.

Design a sequence detector for 1011 (overlapping).

Draw the states S0 (nothing), S1 (1), S2 (10), S3 (101), then output 1 on a 1 from S3 and go to S1 to allow overlap. Then write it with a two-block FSM: one sequential block for the state register, one combinational block for next state and output.

Part 4: FIFOs and CDC

How do you detect full and empty in a synchronous FIFO?

Use pointers one bit wider than the address. Empty when pointers are equal; full when the address bits are equal and the extra wrap bits differ.

Why does an asynchronous FIFO use Gray-coded pointers?

Only one bit changes per increment, so if the other clock domain samples the pointer mid-change it still gets either the old or the new value, never a wrong one.

What is metastability and how do you handle it?

A flop whose input changes inside its setup/hold window can stay between 0 and 1 for an unpredictable time. A two-flop synchroniser gives it a full cycle to settle before use, making failures extremely rare.

Can you synchronise a multi-bit bus with two flops per bit?

No. The bits can resolve on different cycles, giving a value that was never sent. Use a handshake, an async FIFO or Gray code.

How do you calculate FIFO depth?

Depth = worst-case burst minus the words the reader drains while the burst is written. See FIFO depth calculation.

Part 5: Timing

What are setup and hold time?

Setup is how long data must be stable before the clock edge; hold is how long it must stay stable after. Setup violations limit clock frequency; hold violations break the design at any frequency.

How do you fix a setup violation?

Reduce logic depth (pipelining, retiming, restructuring), use faster cells, or lower the clock frequency. In RTL, adding a pipeline stage is the usual fix.

How do you fix a hold violation?

Add delay on the data path, typically buffers inserted during physical design. Changing the clock frequency does not help.

What limits the maximum frequency of a design?

The slowest register-to-register path: clock-to-Q plus logic delay plus setup time, adjusted for clock skew.

Part 6: Resets and low power

Synchronous or asynchronous reset?

Asynchronous resets act immediately without a clock but need a reset synchroniser for clean release; synchronous resets are simpler for timing but need a running clock. Many ASICs use async assert, sync release.

What is clock gating and why use it?

Turning off the clock to idle logic to save dynamic power. It should use an integrated clock-gating cell (latch plus AND) to avoid glitches.

What is a reset domain crossing?

A path from a flop in one reset domain to a flop in another, where an asynchronous reset can cause metastability in the receiver. See RDC explained.

Part 7: How to prepare

• Write each common block from memory: counter, edge detector, FSM, synchronous FIFO, async FIFO, arbiter.
• Practise drawing timing diagrams and explaining them out loud.
• For every answer, prepare one follow-up level deeper.
• Solve problems on a real simulator so you see your mistakes, not just read about them.

FAQ

How should I answer a design question I have never seen?

Clarify the spec, draw a block diagram, state your assumptions, then write the RTL. Interviewers mostly judge how you think, not whether you finish perfectly.

Do RTL interviews include verification questions?

Often a little: how you would test your design, and sometimes basic SystemVerilog or assertions.

Should I write Verilog or SystemVerilog in interviews?

Either is fine; use what you are fluent in. SystemVerilog’s always_ff and always_comb make intent clearer.

How many of these questions should I know?

All of them, with a confident follow-up for each. They are the core that almost every RTL interview builds on.