The short answer: a synchronous reset is sampled on the clock edge like any other input, so it needs a running clock but keeps timing simple. An asynchronous reset takes effect immediately, even without a clock, but its release must be synchronised to avoid recovery and removal problems. Many ASIC teams use the combination: assert reset asynchronously and release it synchronously through a reset synchroniser.
Reset style is one of those topics every team has an opinion on. Here are the facts, so you can choose sensibly and answer the interview question well.
- The two styles compared
- In Verilog
- Detailed comparison
- Releasing reset safely
- What to reset
Table of Contents
Part 1: The two styles compared
Part 2: In Verilog
// Synchronous reset: rst only in the clocked condition
always @(posedge clk)
if (rst) q <= 1'b0;
else q <= d;
// Asynchronous reset: rst in the sensitivity list
always @(posedge clk or posedge rst)
if (rst) q <= 1'b0;
else q <= d;Part 3: Detailed comparison
| Synchronous | Asynchronous | |
|---|---|---|
| Takes effect | Next clock edge | Immediately |
| Clock needed | Yes | No |
| Glitch sensitivity | Filtered by the clock | A reset glitch can reset flops |
| Timing checks | Normal setup and hold | Recovery and removal on release |
| Area | Reset logic in the data path | Uses flops with built-in reset pins |
Part 4: Releasing reset safely
If an asynchronous reset is released close to a clock edge, some flops may leave reset on that edge and others on the next, putting the design in an inconsistent state. A reset synchroniser in each clock domain fixes this by releasing reset on a clean edge. I cover it in detail, with Verilog, in reset domain crossing and reset synchronisers.
Part 5: What to reset
- Reset control state: FSM states, valid bits, counters that control behaviour.
- Datapath registers often do not need a reset if their contents are never used before valid data arrives. Leaving them out saves area, power and routing.
- Be consistent within a block, and follow your team’s reset guidelines.
Practise this on VLSI Forge
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FAQ
Which reset is better?
Neither is always better. Asynchronous assert with synchronous release is a very common choice for ASIC control logic; FPGA designs often prefer synchronous resets.
What are recovery and removal times?
The asynchronous-reset versions of setup and hold: reset must be released far enough from the clock edge for the flop to leave reset cleanly.
Why use active-low reset?
Historically, active-low resets were cheaper and more robust in many technologies, and the convention stuck. Either works if used consistently.
Can I mix reset styles?
Yes, but do it deliberately and document it, especially across clock domains.
