The short answer: a latch is level-sensitive: while its enable is active it is transparent and the output follows the input; when the enable goes inactive it holds the last value. A flip-flop is edge-triggered: it samples its input only at a clock edge. Almost all synchronous designs use flip-flops because their timing is much easier to analyse; latches appear deliberately only in special cases, and accidentally when combinational RTL is written incompletely.
This post combines my older posts on SR latches, D latches and latches vs flip-flops.
- Latch vs flip-flop in one waveform
- The SR latch
- The D latch
- Why designs use flip-flops
- Accidental latches in RTL
Table of Contents
Part 1: Latch vs flip-flop in one waveform
Part 2: The SR latch
The simplest memory element: two cross-coupled NOR gates (or NAND gates). S sets Q to 1, R resets it to 0, and with both inactive it holds its value. With NOR gates, S = R = 1 is not allowed, because it forces both outputs low and the final state is unpredictable when both are released.
Part 3: The D latch
A D latch adds an enable and removes the forbidden state: while EN = 1, Q follows D; when EN = 0, Q holds. In Verilog:
always @(*)
if (en) q = d; // no else: q holds, so this infers a latchPart 4: Why designs use flip-flops
- Edge-triggered timing makes paths start and end at well-defined points, so static timing analysis is simple.
- Latches allow data to race through several stages while enabled, which is useful (time borrowing) but harder to analyse.
- A flip-flop is effectively two latches in a master-slave arrangement on opposite clock phases.
Part 5: Accidental latches in RTL
The most common way latches appear is by mistake: a combinational block that does not assign an output in every path. Synthesis tools warn about inferred latches, and you should treat those warnings as bugs unless you meant it.
// Bug: no else, so 'y' must hold its value -> latch
always @(*) begin
if (sel) y = a;
end
// Fix: assign in every path
always @(*) begin
y = b; // default
if (sel) y = a;
endPractise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
FAQ
Is a latch faster than a flip-flop?
A latch has a shorter delay and allows time borrowing, which some high-performance designs exploit, but it makes timing harder to close.
Why is S = R = 1 forbidden in an SR latch?
It drives both outputs to the same value, and when both inputs are released together the latch can settle to either state.
How do I know if my RTL infers a latch?
Synthesis reports and lint tools flag inferred latches. Check those reports on every run.
Do FPGAs support latches?
Most FPGA flops can be configured as latches, but FPGA timing tools and designs strongly prefer flip-flops.
