The Verilog system tasks I actually use: $display vs $strobe vs $monitor, format specifiers, $finish, file I/O, $readmemh, waveform dumping, $random and $clog2.
Browsing: Verilog programming
Verilog tasks vs functions explained with examples: return values, timing controls, synthesis, how arguments are passed, and static vs automatic.
Verilog templates for flip-flops (async and sync reset, enable), latches, registers, shift registers, pipelines and counters, with rules for sequential blocks.
Verilog if-else, case, casez and loops explained with the hardware they create: priority logic, muxes, unrolled loops, and how to avoid latches.
How Verilog procedural blocks work: initial vs always, event control with @, # and wait, begin-end vs fork-join, and the rules I follow for always blocks in RTL.
Every Verilog operator with examples: bitwise vs logical vs reduction, shifts, concatenation, precedence, expression width, signed arithmetic and what each operator synthesises to.
Verilog data types explained: the four values, nets vs variables, wire vs reg, vectors and part selects, signed types, integer and real, arrays and memories, and implicit nets.