The short answer: AXI interviews focus on the five independent channels, the VALID/READY handshake and its rules, burst types (FIXED, INCR, WRAP) and their limits, the 4 KB boundary rule, byte strobes and unaligned transfers, transaction IDs and ordering, response codes, and the differences between AXI4, AXI4-Lite and AXI4-Stream. Verification roles add protocol assertions and scoreboards; design roles add register slices and interconnects.
AXI is the on-chip bus you’re most likely to meet in an SoC, so it’s the protocol interviewers ask about most, for both design and verification roles. The good news is that most questions come back to a handful of rules.
I use the current AMBA names, manager and subordinate. Older documents and many interviewers still say master and slave; they mean the same thing.
- Channels and handshakes
- Bursts
- IDs, ordering and responses
- Variants, design and verification
Table of Contents
Part 1: Channels and handshakes
1. What is AXI, and where does it fit in AMBA?
AXI (Advanced eXtensible Interface) is Arm’s high-performance on-chip interface, part of the AMBA family. APB is for simple, low-bandwidth peripherals; AHB is an older pipelined bus; AXI is for high-bandwidth, high-concurrency traffic; ACE and CHI add cache coherency for multi-core systems.
2. What are the five AXI channels?
Write address (AW), write data (W), write response (B), read address (AR) and read data (R). Because they’re independent, a manager can issue new addresses while data from earlier transactions is still moving.
3. How does the VALID/READY handshake work?
The source drives VALID when it has information; the destination drives READY when it can accept it. The transfer happens on the rising clock edge where both are high. Either can come first.
4. What are the handshake rules?
- A source must not wait for READY before asserting VALID.
- Once VALID is high, it must stay high, with the payload stable, until the handshake completes.
- A destination may wait for VALID before asserting READY, and may lower READY before VALID arrives.
The first rule is what prevents deadlock: if both sides waited for the other, nothing would ever move.
5. Can write data arrive before the write address?
Yes. AW and W are independent, and a subordinate must handle data arriving first (it may simply hold READY low on W until it sees the address). The write response must come only after the last write data beat, and in AXI4 also after the address handshake.
Part 2: Bursts
6. What burst types does AXI support?
| Burst | Address behaviour | Typical use |
|---|---|---|
| FIXED | Same address every beat | FIFO or peripheral data register |
| INCR | Increments by the transfer size | Normal memory access |
| WRAP | Increments, then wraps at a boundary | Cache line fills (critical word first) |
7. What are the burst length limits?
AxLEN is 8 bits in AXI4, so an INCR burst can be 1 to 256 beats. FIXED and WRAP bursts are limited to 16 beats, and WRAP must be 2, 4, 8 or 16 beats. AXI3 allowed only 1 to 16 beats for all types.
8. What is the 4 KB boundary rule?
A burst must not cross a 4 KB address boundary. The smallest address region a subordinate is given is 4 KB, so this guarantees a burst never splits across two subordinates. Managers (or the logic that splits transactions) must break long bursts at 4 KB.
9. How do you calculate a wrapping burst’s addresses?
The wrap boundary is the start address rounded down to a multiple of (bytes per beat × number of beats). Example: start 0x34, 4 bytes per beat, 4 beats, so 16 bytes total:
wrap boundary = floor(0x34 / 16) * 16 = 0x30
addresses = 0x34, 0x38, 0x3C, 0x3010. What does AxSIZE mean?
The number of bytes in each beat, as a power of two (1, 2, 4 … 128 bytes). It can be smaller than the data bus width; that’s called a narrow transfer, and the active byte lanes change from beat to beat.
11. What are write strobes?
WSTRB has one bit per byte of the write data bus, saying which bytes are valid. They’re used for narrow and unaligned transfers and for partial writes, such as writing one byte of a 32-bit word.
12. How does AXI handle unaligned transfers?
The manager gives the unaligned start address, and the first beat uses strobes to mark only the valid bytes. Later beats are aligned to the transfer size.
Part 3: IDs, ordering and responses
13. What are transaction IDs used for?
Each transaction carries an ID. Transactions with the same ID must complete in order; transactions with different IDs may complete out of order. That lets a fast subordinate respond before a slow one, which improves performance.
14. Is data interleaving allowed?
For reads, yes: read data beats from transactions with different IDs can be interleaved. For writes, no: AXI4 removed write data interleaving (and the WID signal) that AXI3 had.
15. What are the AXI response codes?
OKAY (normal success), EXOKAY (exclusive access succeeded), SLVERR (the subordinate received the access but reports an error) and DECERR (decode error: no subordinate at that address, usually generated by the interconnect).
16. How do exclusive accesses work?
A manager does an exclusive read, then an exclusive write to the same address with the same ID. If nobody else wrote that location in between, the write succeeds with EXOKAY; otherwise it returns OKAY and the location isn’t updated. Software uses it for semaphores and locks.
17. What are outstanding transactions, and why do they matter?
A manager can issue several addresses before earlier transactions complete. With long memory latency, that keeps the bus busy instead of waiting for each response, which is the main reason AXI performs well.
18. What do AxCACHE, AxPROT and AxQOS carry?
AxCACHE says whether a transaction can be buffered, cached or modified on the way; AxPROT carries privilege, security (secure or non-secure) and instruction-or-data information; AxQOS is a priority hint the interconnect can use for arbitration.
Part 4: Variants, design and verification
19. How are AXI4, AXI4-Lite and AXI4-Stream different?
| AXI4 | AXI4-Lite | AXI4-Stream | |
|---|---|---|---|
| Addresses | Yes | Yes | No |
| Bursts | Up to 256 beats | Single beat only | Continuous stream, TLAST marks packets |
| IDs | Yes | No | Optional TID/TDEST |
| Typical use | Memory and high-bandwidth data | Control and status registers | Video, DSP, network data |
20. What is an AXI register slice, and why does a full-throughput one need two entries?
A register slice breaks long timing paths on a channel by registering VALID, payload and READY. If READY is registered, the source can’t see backpressure until a cycle later, so one more beat may arrive; a skid buffer with two entries stores it without losing throughput.
21. What does an AXI interconnect do?
It decodes addresses to route each transaction to the right subordinate, arbitrates between managers, extends IDs so responses get back to the right manager, and often converts widths, clocks or protocols.
22. How would you verify an AXI interface?
- Use a protocol checker or VIP for the handshake and burst rules.
- Build a scoreboard that tracks transactions by ID and checks data and responses.
- Cover burst types, lengths, sizes, unaligned starts, outstanding transactions and backpressure on every channel.
- Include error cases: DECERR on unmapped addresses, SLVERR, and failed exclusives.
23. Write an assertion for the VALID stability rule.
property p_aw_stable;
@(posedge aclk) disable iff (!aresetn)
(awvalid && !awready) |=> (awvalid && $stable(awaddr));
endproperty
a_aw_stable: assert property (p_aw_stable);Practise this on VLSI Forge
I built VLSI Forge so you can write RTL in your browser, run it on a real simulator and check every signal in the waveform. Free, nothing to install.
FAQ
Do I need to read the AMBA AXI specification?
Yes, at least the sections on the handshake, bursts, ordering and responses. Arm publishes it for free, and interviewers often quote it.
Is AXI3 still asked?
Mainly the differences: AXI3 had 16-beat bursts and write data interleaving with WID, both changed in AXI4.
What is the most common AXI interview question?
The VALID/READY rules and why VALID must not wait for READY, followed by the 4 KB boundary and wrap burst addresses.
Should I learn APB as well?
Yes. APB is simple, often used next to AXI for registers, and a common warm-up question.
